Update ChangeLog entry of commit 98c90f8028 and mention PR c++/20020

[external/binutils.git] / opcodes / aarch64-opc-2.c

diff --git a/opcodes/aarch64-opc-2.c b/opcodes/aarch64-opc-2.c
index d6ae4d9..15f2b9f 100644 (file)
--- a/opcodes/aarch64-opc-2.c
+++ b/opcodes/aarch64-opc-2.c
@@ -1,5 +1,5 @@
 /* This file is automatically generated by aarch64-gen.  Do not edit!  */
-/* Copyright (C) 2012-2018 Free Software Foundation, Inc.
+/* Copyright (C) 2012-2019 Free Software Foundation, Inc.
    Contributed by ARM Ltd.
 
    This file is part of the GNU opcodes library.
@@ -112,7 +112,9 @@ const struct aarch64_operand aarch64_operands[] =
   {AARCH64_OPND_CLASS_ADDRESS, "ADDR_SIMM9", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_imm9,FLD_index}, "an address with 9-bit signed immediate offset"},
   {AARCH64_OPND_CLASS_ADDRESS, "ADDR_SIMM9_2", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_imm9,FLD_index}, "an address with 9-bit negative or unaligned immediate offset"},
   {AARCH64_OPND_CLASS_ADDRESS, "ADDR_SIMM10", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn,FLD_S_imm10,FLD_imm9,FLD_index}, "an address with 10-bit scaled, signed immediate offset"},
+  {AARCH64_OPND_CLASS_ADDRESS, "ADDR_SIMM11", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_imm7,FLD_index2}, "an address with 11-bit signed immediate (multiple of 16) offset"},
   {AARCH64_OPND_CLASS_ADDRESS, "ADDR_UIMM12", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn,FLD_imm12}, "an address with scaled, unsigned immediate offset"},
+  {AARCH64_OPND_CLASS_ADDRESS, "ADDR_SIMM13", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_imm9,FLD_index}, "an address with 13-bit signed immediate (multiple of 16) offset"},
   {AARCH64_OPND_CLASS_ADDRESS, "SIMD_ADDR_SIMPLE", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {}, "an address with base register (no offset)"},
   {AARCH64_OPND_CLASS_ADDRESS, "ADDR_OFFSET", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn,FLD_imm9,FLD_index}, "an address with an optional 8-bit signed immediate offset"},
   {AARCH64_OPND_CLASS_ADDRESS, "SIMD_ADDR_POST", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {}, "a post-indexed address with immediate or register increment"},
@@ -230,48 +232,48 @@ const struct aarch64_operand aarch64_operands[] =
 static const unsigned op_enum_table [] =
 {
   0,
-  877,
-  878,
-  879,
-  882,
-  883,
-  884,
-  885,
-  886,
-  880,
-  881,
-  887,
   888,
-  910,
-  911,
-  912,
-  915,
-  916,
-  917,
-  918,
-  919,
-  913,
-  914,
-  920,
+  889,
+  890,
+  893,
+  894,
+  895,
+  896,
+  897,
+  891,
+  892,
+  898,
+  899,
   921,
-  969,
-  970,
-  971,
-  972,
+  922,
+  923,
+  926,
+  927,
+  928,
+  929,
+  930,
+  924,
+  925,
+  931,
+  932,
+  984,
+  985,
+  986,
+  987,
   12,
   636,
   637,
-  1164,
-  1166,
-  1168,
-  976,
-  1167,
-  1165,
+  1179,
+  1181,
+  1183,
+  991,
+  1182,
+  1180,
   318,
   624,
   635,
   634,
-  974,
+  989,
   631,
   628,
   620,
@@ -281,34 +283,34 @@ static const unsigned op_enum_table [] =
   630,
   632,
   633,
-  984,
+  999,
   664,
   667,
   670,
   665,
   668,
-  821,
+  824,
   178,
   179,
   180,
   181,
   516,
-  755,
+  758,
   389,
   391,
   413,
   415,
-  1237,
-  1242,
-  1235,
-  1234,
-  1238,
-  1245,
-  1247,
-  1248,
-  1244,
+  1252,
+  1257,
   1250,
   1249,
+  1253,
+  1260,
+  1262,
+  1263,
+  1259,
+  1265,
+  1264,
   131,
 };