* m68hc11-dis.c (print_insn): Warning fix.

[external/binutils.git] / opcodes / ChangeLog

diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index a36b3cc..e89eb8f 100644 (file)
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,97 @@
+2006-06-06  Alan Modra  <amodra@bigpond.net.au>
+
+       * m68hc11-dis.c (print_insn): Warning fix.
+
+2006-06-05  Daniel Jacobowitz  <dan@codesourcery.com>
+
+       * po/Make-in (top_builddir): Define.
+
+2006-06-05  Alan Modra  <amodra@bigpond.net.au>
+
+       * Makefile.am: Run "make dep-am".
+       * Makefile.in: Regenerate.
+       * config.in: Regenerate.
+
+2006-05-31  Daniel Jacobowitz  <dan@codesourcery.com>
+
+       * Makefile.am (INCLUDES): Use @INCINTL@.
+       * acinclude.m4: Include new gettext macros.
+       * configure.in: Use ZW_GNU_GETTEXT_SISTER_DIR and AM_PO_SUBDIRS.
+       Remove local code for po/Makefile.
+       * Makefile.in, aclocal.m4, configure: Regenerated.
+
+2006-05-30  Nick Clifton  <nickc@redhat.com>
+
+       * po/es.po: Updated Spanish translation.
+
+2006-05-25  Richard Sandiford  <richard@codesourcery.com>
+
+       * m68k-opc.c (m68k_opcodes): Fix the masks of the Coldfire fmovemd
+       and fmovem entries.  Put register list entries before immediate
+       mask entries.  Use "l" rather than "L" in the fmovem entries.
+       * m68k-dis.c (match_insn_m68k): Remove the PRIV argument and work it
+       out from INFO.
+       (m68k_scan_mask): New function, split out from...
+       (print_insn_m68k): ...here.  If no architecture has been set,
+       first try printing an m680x0 instruction, then try a Coldfire one.
+
+2006-05-24  Nick Clifton  <nickc@redhat.com>
+
+       * po/ga.po: Updated Irish translation.
+
+2006-05-22  Nick Clifton  <nickc@redhat.com>
+
+       * crx-dis.c (EXTRACT): Make macro work on 64-bit hosts.
+
+2006-05-22  Nick Clifton  <nickc@redhat.com>
+
+       * po/nl.po: Updated translation.
+
+2006-05-18  Alan Modra  <amodra@bigpond.net.au>
+
+       * avr-dis.c: Formatting fix.
+
+2006-05-14  Thiemo Seufer  <ths@mips.com>
+
+       * mips16-opc.c (I1, I32, I64): New shortcut defines.
+       (mips16_opcodes): Change membership of instructions to their
+       lowest baseline ISA.
+
+2006-05-09  H.J. Lu  <hongjiu.lu@intel.com>
+
+       * i386-dis.c (grps): Update sgdt/sidt for 64bit.
+
+2006-05-05  Julian Brown  <julian@codesourcery.com>
+
+       * arm-dis.c (coprocessor_opcodes): Don't interpret fldmx/fstmx as
+       vldm/vstm.
+
+2006-05-05  Thiemo Seufer  <ths@mips.com>
+            David Ung  <davidu@mips.com>
+
+       * mips-opc.c: Add macro for cache instruction.
+
+2006-05-04  Thiemo Seufer  <ths@mips.com>
+            Nigel Stephens  <nigel@mips.com>
+           David Ung  <davidu@mips.com>
+
+       * mips-dis.c (mips_arch_choices): Add smartmips instruction
+       decoding to MIPS32 and MIPS32R2.  Limit DSP decoding to release
+       2 ISAs.  Add MIPS3D decoding to MIPS32R2.  Add MT decoding to
+       MIPS64R2.
+       * mips-opc.c: fix random typos in comments.
+       (INSN_SMARTMIPS): New defines.
+       (mips_builtin_opcodes): Add paired single support for MIPS32R2.
+       Move bc3f, bc3fl, bc3t, bc3tl downwards.  Move flushi, flushd,
+       flushid, wb upwards.  Move cfc3, ctc3 downwards.  Rework the
+       FP_S and FP_D flags to denote single and double register
+       accesses separately.  Move dmfc3, dmtc3, mfc3, mtc3 downwards.
+       Allow jr.hb and jalr.hb for release 1 ISAs.  Allow luxc1, suxc1
+       for MIPS32R2.  Add SmartMIPS instructions.  Add two-argument
+       variants of bc2f, bc2fl, bc2t, bc2tl.  Add mfhc2, mthc2 to
+       release 2 ISAs.
+       * mips16-opc.c (mips16_opcodes): Add sdbbp instruction.
+
 2006-05-03  Thiemo Seufer  <ths@mips.com>
 
        * mips-opc.c (mips_builtin_opcodes): Fix mftr argument order.