+2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
+
+ * aarch64-asm-2.c: Regenerate.
+ * aarch64-dis-2.c: Regenerate.
+ * aarch64-opc-2.c: Regenerate.
+ * aarch64-tbl.h (QL_ELEMENT_FP_H): New.
+ (aarch64_opcode_table): Add fp16 versions of fmla, fmls, fmul and
+ fmulx to the vector indexed element group.
+
+2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
+
+ * aarch64-asm-2.c: Regenerate.
+ * aarch64-dis-2.c: Regenerate.
+ * aarch64-opc-2.c: Regenerate.
+ * aarch64-tbl.h (QL_SISD_FCMP_H_0): new.
+ (QL_S_2SAMEH): New.
+ (aarch64_opcode_table): Add fp16 versions of fcvtns, fcvtms,
+ fcvtas, scvtf, fcmgt, fcmeq, fcmlt, fcvtps, fcvtzs, frecpe,
+ frecpx, fcvtnu, fcvtmu, fcvtau, ucvtf, fcmge, fcmle, fcvtpu,
+ fcvtzu and frsqrte to the scalar two register misc. group.
+
+2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
+
+ * aarch64-asm-2.c: Regenerate.
+ * aarch64-dis-2.c: Regenerate.
+ * aarch64-opc-2.c: Regenerate.
+ * aarch64-tbl.h (QL_V2SAMEH): New.
+ (aarch64_opcode_table): Add fp16 versions of frintn, frintm,
+ fcvtns, fcvtms, fcvtas, scvtf, fcmgt, fcmeq, fcmlt, fabs, frintp,
+ frintz, fcvtps, fcvtzs, frecpe, frinta, frintx, fcvtnu, fcvtmu,
+ fcvtau, ucvtf, fcmge, fcmle, fneg, frinti, fcvtpu, fcvtzu, frsqrte
+ and fsqrt to the vector register misc. group.
+
+2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
+
+ * aarch64-asm-2.c: Regenerate.
+ * aarch64-dis-2.c: Regenerate.
+ * aarch64-opc-2.c: Regenerate.
+ * aarch64-tbl.h (aarch64_opcode_table): Add fp16 versions of
+ fmulx, fcmeq, frecps, frsqrts, fcmge, facge, fabd, fcmgt and facgt
+ to the scalar three same group.
+
+2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
+
+ * aarch64-asm-2.c: Regenerate.
+ * aarch64-dis-2.c: Regenerate.
+ * aarch64-opc-2.c: Regenerate.
+ * aarch64-tbl.h (QL_V3SAMEH): New.
+ (aarch64_opcode_table): Add fp16 versions of fmaxnm, fmla, fadd,
+ fmulx, fcmeq, fmax, frecps, fminnm, fmls, fsub, fmin, frsqrts,
+ fmaxnmp, faddp, fmul, fcmge, facge, fmaxp, fdiv, fminnmp, fabd,
+ fcmgt, facgt and fminp to the vector three same group.
+
+2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
+
+ * aarch64-tbl.h (aarch64_feature_simd_f16): New.
+ (SIMD_F16): New.
+
+2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
+
+ * aarch64-opc.c (aarch64_sys_reg_supported_p): Add mistakenly
+ removed statement.
+ (aarch64_pstatefield_supported_p): Move feature checks for AT
+ registers ..
+ (aarch64_sys_ins_reg_supported_p): .. to here.
+
+2015-12-12 Alan Modra <amodra@gmail.com>
+
+ PR 19359
+ * ppc-opc.c (insert_fxm): Remove "ignored" from error message.
+ (powerpc_opcodes): Remove single-operand mfcr.
+
+2015-12-11 Matthew Wahab <matthew.wahab@arm.com>
+
+ * aarch64-asm.c (aarch64_ins_hint): New.
+ * aarch64-asm.h (aarch64_ins_hint): Declare.
+ * aarch64-dis.c (aarch64_ext_hint): New.
+ * aarch64-dis.h (aarch64_ext_hint): Declare.
+ * aarch64-opc-2.c: Regenerate.
+ * aarch64-opc.c (aarch64_hint_options): New.
+ * aarch64-tbl.h (AARCH64_OPERANDS): Fix typos.
+
+2015-12-11 Matthew Wahab <matthew.wahab@arm.com>
+
+ * aarch64-gen.c (find_alias_opcode): Set max_num_aliases to 16.
+
+2015-12-11 Matthew Wahab <matthew.wahab@arm.com>
+
+ * aarch64-opc.c (aarch64_sys_reg): Add pbmlimitr_el1, pmbptr_el1,
+ pmbsr_el1, pmbidr_el1, pmscr_el1, pmsicr_el1, pmsirr_el1,
+ pmsfcr_el1, pmsevfr_el1, pmslatfr_el1, pmsidr_el1, pmscr_el2 and
+ pmscr_el2.
+ (aarch64_sys_reg_supported_p): Add architecture feature tests for
+ the new registers.
+
+2015-12-10 Matthew Wahab <matthew.wahab@arm.com>
+
+ * aarch64-opc.c (aarch64_sys_regs_at): Add "s1e1rp" and "s1e1wp".
+ (aarch64_sys_ins_reg_supported_p): Add ARMv8.2 system register
+ feature test for "s1e1rp" and "s1e1wp".
+
+2015-12-10 Matthew Wahab <matthew.wahab@arm.com>
+
+ * aarch64-opc.c (aarch64_sys_regs_dc): Add "cvap".
+ (aarch64_sys_ins_reg_supported_p): New.
+
+2015-12-10 Matthew Wahab <matthew.wahab@arm.com>
+
+ * aarch64-dis.c (aarch64_ext_regrt_sysins): Replace use of has_xt
+ with aarch64_sys_ins_reg_has_xt.
+ (aarch64_ext_sysins_op): Likewise.
+ * aarch64-opc.c (operand_general_constraint_met_p): Likewise.
+ (F_HASXT): New.
+ (aarch64_sys_regs_ic): Update for changes to aarch64_sys_ins_reg.
+ (aarch64_sys_regs_dc): Likewise.
+ (aarch64_sys_regs_at): Likewise.
+ (aarch64_sys_regs_tlbi): Likewise.
+ (aarch64_sys_ins_reg_has_xt): New.
+
+2015-12-10 Matthew Wahab <matthew.wahab@arm.com>
+
+ * aarch64-opc.c (aarch64_sys_regs): Add "uao".
+ (aarch64_sys_reg_supported_p): Add comment. Add checks for "uao".
+ (aarch64_pstatefields): Add "uao".
+ (aarch64_pstatefield_supported_p): Add checks for "uao".
+
+2015-12-10 Matthew Wahab <matthew.wahab@arm.com>
+
+ * aarch64-opc.c (aarch64_sys_regs): Add "vsesr_el2", "erridr_el1",
+ "errselr_el1", "erxfr_el1", "erxctlr", "erxaddr_el1",
+ "erxmisc0_el1", "erxmisc1_el1", "disr_el1" and "vdisr_el2".
+ (aarch64_sys_reg_supported_p): Add architecture feature tests for
+ new registers.
+
+2015-12-10 Matthew Wahab <matthew.wahab@arm.com>
+
+ * aarch64-asm-2.c: Regenerate.
+ * aarch64-dis-2.c: Regenerate.
+ * aarch64-tbl.h (aarch64_feature_ras): New.
+ (RAS): New.
+ (aarch64_opcode_table): Add "esb".
+
+2015-12-09 H.J. Lu <hongjiu.lu@intel.com>
+
+ * i386-dis.c (MOD_0F01_REG_5): New.
+ (RM_0F01_REG_5): Likewise.
+ (reg_table): Use MOD_0F01_REG_5.
+ (mod_table): Add MOD_0F01_REG_5.
+ (rm_table): Add RM_0F01_REG_5.
+ * i386-gen.c (cpu_flag_init): Add CPU_OSPKE_FLAGS.
+ (cpu_flags): Add CpuOSPKE.
+ * i386-opc.h (CpuOSPKE): New.
+ (i386_cpu_flags): Add cpuospke.
+ * i386-opc.tbl: Add rdpkru and wrpkru instructions.
+ * i386-init.h: Regenerated.
+ * i386-tbl.h: Likewise.
+
+2015-12-07 DJ Delorie <dj@redhat.com>
+
+ * rl78-decode.opc: Enable MULU for all ISAs.
+ * rl78-decode.c: Regenerate.
+
+2015-12-07 Alan Modra <amodra@gmail.com>
+
+ * opcodes/ppc-opc.c (powerpc_opcodes): Sort power9 insns by
+ major opcode/xop.
+
+2015-12-04 Claudiu Zissulescu <claziss@synopsys.com>
+
+ * arc-dis.c (special_flag_p): Match full mnemonic.
+ * arc-opc.c (print_insn_arc): Check section size to read
+ appropriate number of bytes. Fix printing.
+ * arc-tbl.h: Fix instruction table. Allow clri/seti instruction without
+ arguments.
+
+2015-12-02 Andre Vieira <andre.simoesdiasvieira@arm.com>
+
+ * arm-dis.c (arm_opcodes): <ldaexh>: Fix typo...
+ <ldah>: ... to this.
+
+2015-11-27 Matthew Wahab <matthew.wahab@arm.com>
+
+ * aarch64-asm-2.c: Regenerate.
+ * aarch64-dis-2.c: Regenerate.
+ * aarch64-opc-2.c: Regenerate.
+ * aarch64-tbl.h (QL_FIX2FP_H, QL_FP2FIX_H): New.
+ (QL_INT2FP_H, QL_FP2INT_H): New.
+ (QL_FP2_H, QL_FP3_H, QL_FP4_H): New
+ (QL_DST_H): New.
+ (QL_FCCMP_H): New.
+ (aarch64_opcode_table): Add 16-bit variants of scvt, ucvtf,
+ fcvtzs, fcvtzu, fcvtns, fcvtnu, scvtf, ucvtf, fcvtas, fcvtau,
+ fmov, fcvtpos, fcvtpu, fcvtms, fcvtmu, fcvtzs, fcvtzu, fccmp,
+ fccmpe, fcmp, fcmpe, fabs, fneg, fsqrt, frintn, frintp, frintm,
+ frintz, frinta, frintx, frinti, fmul, fdiv, fadd, fsub, fmax,
+ fmin, fmaxnm, fminnm, fnmul, fmadd, fmsub, fnmadd, fnmsub and
+ fcsel.
+
+2015-11-27 Matthew Wahab <matthew.wahab@arm.com>
+
+ * aarch64-opc.c (half_conv_t): New.
+ (expand_fp_imm): Replace is_dp flag with the parameter size to
+ specify the number of bytes for the required expansion. Treat
+ a 16-bit expansion like a 32-bit expansion. Add check for an
+ unsupported size request. Update comment.
+ (aarch64_print_operand): Update to support 16-bit floating point
+ values. Update for changes to expand_fp_imm.
+
+2015-11-27 Matthew Wahab <matthew.wahab@arm.com>
+
+ * aarch64-tbl.h (aarch64_feature_fp_f16): New.
+ (FP_F16): New.
+
+2015-11-27 Matthew Wahab <matthew.wahab@arm.com>
+
+ * aarch64-asm-2.c: Regenerate.
+ * aarch64-dis-2.c: Regenerate.
+ * aarch64-opc-2.c: Regenerate.
+ * aarch64-tbl.h (aarchr64_opcode_table): Update "rev", add
+ "rev64".
+
+2015-11-27 Matthew Wahab <matthew.wahab@arm.com>
+
+ * aarch64-asm-2.c: Regenerate.
+ * aarch64-asm.c (convert_bfc_to_bfm): New.
+ (convert_to_real): Add case for OP_BFC.
+ * aarch64-dis-2.c: Regenerate.
+ * aarch64-dis.c: (convert_bfm_to_bfc): New.
+ (convert_to_alias): Add case for OP_BFC.
+ * aarch64-opc-2.c: Regenerate.
+ * aarch64-opc.c (operand_general_constraint_met_p): Weaken assert
+ to allow width operand in three-operand instructions.
+ * aarch64-tbl.h (QL_BF1): New.
+ (aarch64_feature_v8_2): New.
+ (ARMV8_2): New.
+ (aarch64_opcode_table): Add "bfc".
+
+2015-11-27 Matthew Wahab <matthew.wahab@arm.com>
+
+ * aarch64-asm-2.c: Regenerate.
+ * aarch64-dis-2.c: Regenerate.
+ * aarch64-dis.c: Weaken assert.
+ * aarch64-gen.c: Include the instruction in the list of its
+ possible aliases.
+
+2015-11-27 Matthew Wahab <matthew.wahab@arm.com>
+
+ * aarch64-opc.c (aarch64_sys_regs): Add "id_aa64mmfr2_el1".
+ (aarch64_sys_reg_supported_p): Add ARMv8.2 system register
+ feature test.
+
+2015-11-23 Tristan Gingold <gingold@adacore.com>
+
+ * arm-dis.c (print_insn): Also set is_thumb for Mach-O.
+
+2015-11-20 Matthew Wahab <matthew.wahab@arm.com>
+
+ * aarch64-opc.c (aarch64_sys_regs): Add spsr_el12, elr_el12,
+ sctlr_el12, cpacr_el12, ttbr1_el2, ttbr0_el12, ttbr1_el12,
+ tcr_el12, afsr0_el12, afsr1_el12, esr_el12, far_el12, mair_el12,
+ amair_el12, vbar_el12, contextidr_el2, contextidr_el12,
+ cntkctl_el12, cntp_tval_el02, cntp_ctl_el02, cntp_cval_el02,
+ cntv_tval_el02, cntv_ctl_el02, cntv_cval_el02, cnthv_tval_el2,
+ cnthv_ctl_el2, cnthv_cval_el2.
+ (aarch64_sys_reg_supported_p): Update for the new system
+ registers.
+
+2015-11-20 Nick Clifton <nickc@redhat.com>
+
+ PR binutils/19224
+ * h8300-dis.c (bfd_h8_disassemble): Remove redundant if clause.
+
+2015-11-20 Nick Clifton <nickc@redhat.com>
+
+ * po/zh_CN.po: Updated simplified Chinese translation.
+
+2015-11-19 Matthew Wahab <matthew.wahab@arm.com>
+
+ * aarch64-opc.c (operand_general_constraint_met_p): Check validity
+ of MSR PAN immediate operand.
+
+2015-11-16 Nick Clifton <nickc@redhat.com>
+
+ * rx-dis.c (condition_names): Replace always and never with
+ invalid, since the always/never conditions can never be legal.
+
+2015-11-13 Tristan Gingold <gingold@adacore.com>
+
+ * configure: Regenerate.
+
+2015-11-11 Alan Modra <amodra@gmail.com>
+ Peter Bergner <bergner@vnet.ibm.com>
+
+ * ppc-dis.c (ppc_opts): Add "power9" and "pwr9" entries.
+ Add PPC_OPCODE_VSX3 to the vsx entry.
+ (powerpc_init_dialect): Set default dialect to power9.
+ * ppc-opc.c (insert_dcmxs, extract_dcmxs, insert_dxd, extract_dxd,
+ insert_dxdn, extract_dxdn, insert_l0, extract_l0, insert_l1,
+ extract_l1 insert_xtq6, extract_xtq6): New static functions.
+ (insert_esync): Test for illegal L operand value.
+ (DCMX, DCMXS, DXD, NDXD, L0, L1, RC, FC, UIM6, X_R, RIC, PRS, XSQ6,
+ XTQ6, LRAND, IMM8, DQX, DQX_MASK, DX, DX_MASK, VXVAPS_MASK, VXVA,XVA,
+ XX2VA, XVARC, XBF_MASK, XX2UIM4_MASK, XX2BFD_MASK, XX2DCMXS_MASK,
+ XVA_MASK, XRLA_MASK, XBFRARB_MASK, XLRAND_MASK, POWER9, PPCVEC3,
+ PPCVSX3): New defines.
+ (powerpc_opcodes) <ps_cmpu0, ps_cmpo0, ps_cmpu1, ps_cmpo1, fcmpu,
+ fcmpo, ftdiv, ftsqrt>: Use XBF_MASK.
+ <mcrxr>: Use XBFRARB_MASK.
+ <addpcis, bcdcfn., bcdcfsq., bcdcfz., bcdcpsgn., bcdctn., bcdctsq.,
+ bcdctz., bcds., bcdsetsgn., bcdsr., bcdtrunc., bcdus., bcdutrunc.,
+ cmpeqb, cmprb, cnttzd, cnttzd., cnttzw, cnttzw., copy, copy_first,
+ cp_abort, darn, dtstsfi, dtstsfiq, extswsli, extswsli., ldat, ldmx,
+ lwat, lxsd, lxsibzx, lxsihzx, lxssp, lxv, lxvb16x, lxvh8x, lxvl, lxvll,
+ lxvwsx, lxvx, maddhd, maddhdu, maddld, mcrxrx, mfvsrld, modsd, modsw,
+ modud, moduw, msgsync, mtvsrdd, mtvsrws, paste, paste., paste_last,
+ rmieg, setb, slbieg, slbsync, stdat, stop, stwat, stxsd, stxsibx,
+ stxsihx, stxssp, stxv, stxvb16x, stxvh8x, stxvl, stxvll, stxvx,
+ subpcis, urfid, vbpermd, vclzlsbb, vcmpneb, vcmpneb., vcmpneh,
+ vcmpneh., vcmpnew, vcmpnew., vcmpnezb, vcmpnezb., vcmpnezh, vcmpnezh.,
+ vcmpnezw, vcmpnezw., vctzb, vctzd, vctzh, vctzlsbb, vctzw, vextractd,
+ vextractub, vextractuh, vextractuw, vextsb2d, vextsb2w, vextsh2d,
+ vextsh2w, vextsw2d, vextublx, vextubrx, vextuhlx, vextuhrx, vextuwlx,
+ vextuwrx, vinsertb, vinsertd, vinserth, vinsertw, vmul10cuq,
+ vmul10ecuq, vmul10euq, vmul10uq, vnegd, vnegw, vpermr, vprtybd,
+ vprtybq, vprtybw, vrldmi, vrldnm, vrlwmi, vrlwnm, vslv, vsrv, wait,
+ xsabsqp, xsaddqp, xsaddqpo, xscmpeqdp, xscmpexpdp, xscmpexpqp,
+ xscmpgedp, xscmpgtdp, xscmpnedp, xscmpoqp, xscmpuqp, xscpsgnqp,
+ xscvdphp, xscvdpqp, xscvhpdp, xscvqpdp, xscvqpdpo, xscvqpsdz,
+ xscvqpswz, xscvqpudz, xscvqpuwz, xscvsdqp, xscvudqp, xsdivqp,
+ xsdivqpo, xsiexpdp, xsiexpqp, xsmaddqp, xsmaddqpo, xsmaxcdp,
+ xsmaxjdp, xsmincdp, xsminjdp, xsmsubqp, xsmsubqpo, xsmulqp, xsmulqpo,
+ xsnabsqp, xsnegqp, xsnmaddqp, xsnmaddqpo, xsnmsubqp, xsnmsubqpo,
+ xsrqpi, xsrqpix, xsrqpxp, xssqrtqp, xssqrtqpo, xssubqp, xssubqpo,
+ xststdcdp, xststdcqp, xststdcsp, xsxexpdp, xsxexpqp, xsxsigdp,
+ xsxsigqp, xvcmpnedp, xvcmpnedp., xvcmpnesp, xvcmpnesp., xvcvhpsp,
+ xvcvsphp, xviexpdp, xviexpsp, xvtstdcdp, xvtstdcsp, xvxexpdp,
+ xvxexpsp, xvxsigdp, xvxsigsp, xxbrd, xxbrh, xxbrq, xxbrw, xxextractuw,
+ xxinsertw, xxperm, xxpermr, xxspltib>: New instructions.
+ <doze, nap, sleep, rvwinkle, waitasec, lxvx, stxvx>: Disable on POWER9.
+ <tlbiel, tlbie, sync, slbmfev, slbmfee>: Add additional operands.
+
+2015-11-02 Nick Clifton <nickc@redhat.com>
+
+ * rx-decode.opc (rx_decode_opcode): Decode extra NOP
+ instructions.
+ * rx-decode.c: Regenerate.
+
+2015-11-02 Nick Clifton <nickc@redhat.com>
+
+ * rx-decode.opc (rx_disp): If the displacement is zero, set the
+ type to RX_Operand_Zero_Indirect.
+ * rx-decode.c: Regenerate.
+ * rx-dis (print_insn): Handle RX_Operand_Zero_Indirect.
+
+2015-10-28 Yao Qi <yao.qi@linaro.org>
+
+ * aarch64-dis.c (aarch64_decode_insn): Add one argument
+ noaliases_p. Update comments. Pass noaliases_p rather than
+ no_aliases to aarch64_opcode_decode.
+ (print_insn_aarch64_word): Pass no_aliases to
+ aarch64_decode_insn.
+
+2015-10-27 Vinay <Vinay.G@kpit.com>
+
+ PR binutils/19159
+ * rl78-decode.opc (MOV): Added offset to DE register in index
+ addressing mode.
+ * rl78-decode.c: Regenerate.
+
+2015-10-27 Vinay Kumar <vinay.g@kpit.com>
+
+ PR binutils/19158
+ * rl78-decode.opc: Add 's' print operator to instructions that
+ access system registers.
+ * rl78-decode.c: Regenerate.
+ * rl78-dis.c (print_insn_rl78_common): Decode all system
+ registers.
+
2015-10-27 Vinay Kumar <vinay.g@kpit.com>
PR binutils/19157
projects / external / binutils.git / blobdiff