+Wed Jan 14 17:37:03 1998 Nick Clifton <nickc@cygnus.com>
+
+ * m32r-dis.in: Generated file imported from cgen.
+ * cgen-asm.in: Formatting changes to improve readability.
+ * m32r-asm.c: Formatting changes to improve readability.
+ * cgen-dis.c: Formatting changes to improve readability.
+ * m32r-dis.c: Add support for disassembling parallel
+ instructions.
+ * m32r-opc.h: Update with latest version generated by cgen.
+ * m32r-opc.c: Update with latest version generated by cgen, plus
+ hand patches to allow attributes to work until cgen can generate
+ these correctly.
+
+start-sanitize-r5900
+Tue Jan 13 09:21:56 1998 Jeffrey A Law (law@cygnus.com)
+
+ * mips-opc.c (c.lt.s): Add r5900 variant.
+ (c.le.s): Likewise.
+
+end-sanitize-r5900
+Mon Jan 12 14:43:54 1998 Doug Evans <devans@seba.cygnus.com>
+
+ * cgen-asm.c (build_asm_hash_table): Traverse compiled in table using
+ table provided entry size. Use CGEN_INSN_MNEMONIC.
+ (cgen_parse_keyword): Rewrite.
+ * cgen-dis.c (build_dis_hash_table): Traverse compiled in table using
+ table provided entry size. Use CGEN_INSN_MASK_BITSIZE.
+ * cgen-opc.c: Clean up pass over `struct foo' usage.
+ (cgen_keyword_lookup_value): Handle "" entry.
+ (cgen_keyword_add): Likewise.
+start-sanitize-cygnus
+ * Makefile.am: Add cgen support.
+ * Makefile.in: Regenerate.
+ * configure.in: Add cgen support.
+ * configure: Regenerate.
+ * aclocal.m4: Regenerate.
+ * cgen.sh, cgen-asm.in, cgen-dis.in: New files.
+end-sanitize-cygnus
+
+start-sanitize-sky
+Tue Jan 6 13:08:14 1998 Doug Evans <devans@seba.cygnus.com>
+
+ * txvu-dis.c (print_insn_txvu): Handle no separator between
+ upper and lower insn #ifndef VERTICAL_BAR_SEPARATOR.
+
+Mon Jan 5 13:41:07 1998 Doug Evans <devans@seba.cygnus.com>
+
+ * txvu-dis.c, txvu-opc.c: New files.
+ * configure.in: Compile them.
+ * configure: Regenerate.
+ * Makefile.am (ALL_MACHINES): Add txvu-{dis,opc}.lo.
+ (txvu-dis.lo,txvu-opc.lo): Add rules for.
+ * Makefile.in: Regenerate.
+
+Mon Dec 22 17:17:03 1997 Doug Evans <devans@canuck.cygnus.com>
+
+ * configure.in: Add txvu support.
+ * configure: Regenerate.
+ * disassemble.c: Add txvu support.
+
+end-sanitize-sky
+Mon Dec 22 12:37:06 1997 Ian Lance Taylor <ian@cygnus.com>
+
+ * mips-opc.c: Add FP_D to s.d instruction flags.
+
+Wed Dec 17 11:38:29 1997 Andreas Schwab <schwab@issan.informatik.uni-dortmund.de>
+
+ * m68k-opc.c (halt, pulse): Enable them on the 68060.
+
+start-sanitize-tic80
+Tue Dec 16 15:22:53 1997 Fred Fish <fnf@cygnus.com>
+
+ * tic80-opc.c (tic80_opcodes): Revert change that put the 32 bit
+ PC relative offset forms before the 15 bit forms. An assembler command
+ line option now chooses the default.
+
+end-sanitize-tic80
+start-sanitize-r5900
+Tue Dec 16 13:24:22 1997 Jeffrey A Law (law@cygnus.com)
+
+ * mips-opc.c: Add many missing r5900 instructions.
+
+end-sanitize-r5900
+start-sanitize-r5900
+Tue Dec 16 15:22:51 1997 Michael Meissner <meissner@cygnus.com>
+
+ * d30v-opc.c (d30v_opcode_table): Set new flags bits
+ FLAG_{2WORD,MUL{16,32},ADDSUBppp}, in appropriate instructions.
+
+end-sanitize-r5900
+1997-12-15 Brendan Kehoe <brendan@lisa.cygnus.com>
+
+ * configure: Only build libopcodes shared if --enable-shared's value
+ was `yes', or was set to `*opcodes*'.
+ * aclocal.m4: Likewise.
+ * NOTE: this really needs to be fixed in libtool/libtool.m4, the
+ original source of this bit of code. It's not clear what the best fix
+ would be, though.
+
+start-sanitize-r5900
+Mon Dec 15 12:43:36 1997 Jeffrey A Law (law@cygnus.com)
+
+ * mips-opc.c (mtpc, mfpc, mtps, mfps): Add r5900 variants.
+end-sanitize-r5900
+start-sanitize-tic80
+Fri Dec 12 11:57:04 1997 Fred Fish <fnf@cygnus.com>
+
+ * tic80-opc.c (OFF_SL_PC, OFF_SL_BR): Minor formatting change.
+ (tic80_opcodes): Reorder table entries to put the 32 bit PC relative
+ offset forms before the 15 bit forms, to default to the long forms.
+
+end-sanitize-tic80
+Fri Dec 12 01:32:30 1997 Richard Henderson <rth@cygnus.com>
+
+ * alpha-opc.c (cvttq/*u*): Remove, as that suffix is invalid.
+
+Wed Dec 10 17:42:35 1997 Nick Clifton <nickc@cygnus.com>
+
+ * arm-dis.c (print_insn_little_arm): Prevent examination of stored
+ symbol if none is present.
+ (print_insn_big_arm): Prevent examination of stored symbol if
+ none is present.
+
+Thu Oct 23 21:13:37 1997 Fred Fish <fnf@cygnus.com>
+
+ * d10v-opc.c (d10v_opcodes): Correct entry for RTE.
+
+Mon Dec 8 11:21:07 1997 Nick Clifton <nickc@cygnus.com>
+
+ * disassemble.c: Remove disasm_symaddr() function.
+
+ * arm-dis.c: Use info->symbol instead of info->flags to determine
+ if disassmbly should be in Thumb or Arm mode.
+
+Tue Dec 2 09:54:27 1997 Nick Clifton <nickc@cygnus.com>
+
+ * arm-dis.c: Add support for disassembling Thumb opcodes.
+ (print_insn_thumb): New function.
+
+ * disassemble.c (disasm_symaddr): New function.
+
+ * arm-opc.h: Display nop pseudo ops alongside equivalent disassembly.
+ (thumb_opcodes): Table of Thumb opcodes.
+
+Mon Dec 1 12:25:57 1997 Andreas Schwab <schwab@issan.informatik.uni-dortmund.de>
+
+ * m68k-opc.c (btst): Change Dd@s to Dd;b.
+
+ * m68k-dis.c (print_insn_arg): Recognize 'm', 'n', 'o', 'p', 'q',
+ and 'v' as operand types.
+
+Mon Dec 1 11:56:50 1997 Ian Lance Taylor <ian@cygnus.com>
+
+ * m68k-opc.c: Add argument for lpstop. From Olivier Carmona
+ <olivier.carmona@di.epfl.ch>.
+ * m68k-dis.c (print_insn_m68k): Handle special case of lpstop,
+ which has a two word opcode with a one word argument.
+
+start-sanitize-d30v
+Sun Nov 23 22:25:21 1997 Michael Meissner <meissner@cygnus.com>
+
+ * d30v-opc.c (d30v_opcode_table, case cmpu): Immediate field is
+ unsigned, not signed.
+ (d30v_format_table): Add SHORT_CMPU cases for cmpu.
+
+end-sanitize-d30v
+start-sanitize-sh4
+Wed Nov 19 17:42:35 1997 Richard Henderson <rth@cygnus.com>
+
+ * sh-dis.c (print_insn_shx): Recognize all sh4 additions.
+ * sh-opc.h (fmov): Add @<REG_M>+,<DX_REG_N> variant for sh4.
+ (ftrv): Slay the cut-and-paste monster.
+
+end-sanitize-sh4
+Tue Nov 18 23:10:03 1997 J"orn Rennecke <amylaar@cygnus.co.uk>
+
+ * d10v-dis.c (print_operand):
+ Split OPERAND_FLAG into OPERAND_FFLAG and OPERAND_CFLAG.
+
+Tue Nov 18 18:45:14 1997 J"orn Rennecke <amylaar@cygnus.co.uk>
+
+ * d10v-opc.c (OPERAND_FLAG): Split into:
+ (OPERAND_FFLAG, OPERAND_CFLAG) .
+ (FSRC): Split into:
+ (FFSRC, CFSRC).
+
+Thu Nov 13 11:05:33 1997 Gavin Koch <gavin@cygnus.com>
+
+ * mips-opc.c: Move the INSN_MACRO ISA value to the membership
+ field for all INSN_MACRO's.
+ * mips16-opc.c: same
+
+Wed Nov 12 10:16:57 1997 Gavin Koch <gavin@cygnus.com>
+
+ * mips-opc.c (sync,cache): These are 3900 insns.
+
+Tue Nov 11 23:53:41 1997 J"orn Rennecke <amylaar@cygnus.co.uk>
+
+ sh-opc.h (sh_table): Remove ftst/nan.
+
+start-sanitize-vr5400
+Mon Nov 3 13:23:15 1997 Ken Raeburn <raeburn@cygnus.com>
+
+ * mips-opc.c (dror32, dror, rzu.ob): Fix bugs in encoding.
+ (c.*.ob, mula.ob, mull.ob, muls.ob, mulsl.ob): Put 'k' version
+ last.
+ * mips-dis.c (print_insn_arg): Handle VR5400 operand types.
+
+end-sanitize-vr5400
+start-sanitize-tx49
+Wed Oct 29 15:10:56 1997 Gavin Koch <gavin@cygnus.com>
+
+ * mips-opc.c (deret,dmult,dmultu,madd,maddu,pref,sdbbp):
+ Add tx49 insns and configury.
+
+end-sanitize-tx49
+Tue Oct 28 17:59:32 1997 Ken Raeburn <raeburn@cygnus.com>
+
+ * mips-opc.c (ffc, ffs): Fix mask.
+
+start-sanitize-d30v
+Tue Oct 28 16:34:54 1997 Michael Meissner <meissner@cygnus.com>
+
+ * d30v-opc.c (pre_defined_registers): Add eit_vb, int_s, and int_m
+ control registers.
+
+end-sanitize-d30v
+Mon Oct 27 22:34:03 1997 Ken Raeburn <raeburn@cygnus.com>
+
+ * mips-opc.c: Fix bug in mask for "not" pseudo-instruction.
+start-sanitize-vr5400
+ Added VR5400 instructions.
+ (N5): New cpu-id macro.
+end-sanitize-vr5400
+ (WR_HILO, RD_HILO, MOD_HILO): New macros.
+
+Mon Oct 27 22:34:03 1997 Ken Raeburn <raeburn@cygnus.com>
+
+ * mips-opc.c: Fix bug in mask for "not" pseudo-instruction.
+ (WR_HILO, RD_HILO, MOD_HILO): New macros.
+
+Thu Oct 23 14:57:58 1997 Nick Clifton <nickc@cygnus.com>
+
+ * v850-dis.c (disassemble): Replace // with /* ... */
+
+Wed Oct 22 17:33:21 1997 Richard Henderson <rth@cygnus.com>
+
+ * sparc-opc.c: Add wr & rd for v9a asr's.
+ * sparc-dis.c (print_insn_sparc): Recognize '_' and '/' for v9a asr's.
+ (v9a_asr_reg_names): New variable.
+ Patch from David Miller <davem@vger.rutgers.edu>.
+
+Wed Oct 22 17:18:02 1997 Richard Henderson <rth@cygnus.com>
+
+ * sparc-opc.c (v9notv9a): New insn type.
+ (IMPDEP): Move to the end to not conflict with edge8 et al.
+ Patch from David Miller <davem@vger.rutgers.edu>.
+
+Fri Oct 17 13:18:53 1997 Gavin Koch <gavin@cygnus.com>
+
+ * mips-opc.c (bnezl,beqzl): Mark these as also tx39.
+
+Thu Oct 16 11:55:20 1997 Gavin Koch <gavin@cygnus.com>
+
+ * mips-opc.c: Note that 'jalx' is (probably incorrectly) marked I1.
+
+Tue Oct 14 16:10:31 1997 Nick Clifton <nickc@cygnus.com>
+
+ * v850-dis.c (disassemble): Use new symbol_at_address_func() field
+ of disassemble_info structure to determine if an overlay address
+ has a matching symbol in low memory.
+
+ * dis-buf.c (generic_symbol_at_address): New (dummy) function for
+ new symbol_at_address_func field in disassemble_info structure.
+
+Fri Oct 10 16:44:52 1997 Nick Clifton <nickc@cygnus.com>
+
+ * v850-opc.c (extract_d22): Use signed arithmatic.
+
+Tue Oct 7 23:40:43 1997 Gavin Koch <gavin@cygnus.com>
+
+ * mips-opc.c: Three op mult is not an ISA insn.
+
+Tue Oct 7 23:37:21 1997 Gavin Koch <gavin@cygnus.com>
+
+ * mips-opc.c: Fix formatting.
+
+Fri Oct 3 17:26:54 1997 Ian Lance Taylor <ian@cygnus.com>
+
+ * i386-dis.c (OP_E): Explicitly sign extend 8 bit values, rather
+ than assuming that char is signed. Explicitly sign extend 16 bit
+ values, rather than assuming that short is 16 bits.
+ (OP_sI, OP_J, OP_DIR): Likewise.
+
+start-sanitize-v850e
+Thu Oct 2 13:36:45 1997 Nick Clifton <nickc@cygnus.com>
+
+ * v850-dis.c (v850_sreg_names): Use symbolic names for higher
+ system registers.
+
+end-sanitize-v850e
+Wed Oct 1 16:58:54 1997 Nick Clifton <nickc@cygnus.com>
+
+ * v850-opc.c: Fix typo in comment.
+
+ * v850-dis.c (disassemble): Add test of processor type when
+ determining opcodes.
+
+Wed Oct 1 14:10:20 1997 Ian Lance Taylor <ian@cygnus.com>
+
+ * configure.in: Use a diversion to set enable_shared before the
+ arguments are parsed.
+ * configure: Rebuild.
+
+Thu Sep 25 13:04:59 1997 Ian Lance Taylor <ian@cygnus.com>
+
+ * m68k-opc.c (TBL1): Use ! rather than `.
+ * m68k-dis.c (print_insn_arg): Remove ` operand specifier.
+
+Wed Sep 24 11:29:35 1997 Ian Lance Taylor <ian@cygnus.com>
+
+ * m68k-opc.c: Correct bchg, bclr, bset, and btst on ColdFire.
+
+ * m68k-opc.c: Accept tst{b,w,l} with immediate operands on cpu32.
+
+ * m68k-opc.c: Correct movew of an immediate operand to %sr or %ccr
+ for mcf5200.
+
+ * configure.in: Call AC_CHECK_TOOL before AM_PROG_LIBTOOL.
+ * aclocal.m4: Rebuild with new libtool.
+ * configure: Rebuild.
+
+start-sanitize-v850e
+Fri Sep 19 11:45:49 1997 Andrew Cagney <cagney@b1.cygnus.com>
+
+ * v850-opc.c ("cmov"): Order reg param r1, r2 not r2, r2.
+
+end-sanitize-v850e
+Thu Sep 18 11:21:43 1997 Doug Evans <dje@canuck.cygnus.com>
+
+ * sparc-opc.c (sparclet_cpreg_table): Add %ccsr2, %cccrr, %ccrstr.
+
+Tue Sep 16 15:18:20 1997 Nick Clifton <nickc@cygnus.com>
+
+ * v850-opc.c (v850_opcodes): Further rearrangements.
+
+start-sanitize-d30v
+Tue Sep 16 16:12:11 1997 Ken Raeburn <raeburn@cygnus.com>
+
+ * d30v-opc.c (rot2h, sra2h, srl2h insns): Revert last change.
+
+end-sanitize-d30v
+Tue Sep 16 09:48:50 1997 Nick Clifton <nickc@cygnus.com>
+
+ * v850-opc.c (v850_opcodes): Fields reordered to allow assembler
+ parser to work.
+
+Tue Sep 16 10:01:00 1997 Gavin Koch <gavin@cygnus.com>
+
+ * mips-opc.c: Added tx39 insns sdbbp, rfe, and deret.
+start-sanitize-tx19
+ * mips16-opc.c: Added mips16 sdbbp.
+end-sanitize-tx19
+
+Mon Sep 15 18:31:52 1997 Nick Clifton <nickc@cygnus.com>
+
+ * v850-opc.c: Initialise processors field of v850_opcode structure.
+
+start-sanitize-d30v
+Wed Aug 27 21:42:39 1997 Ken Raeburn <raeburn@cygnus.com>
+
+ Merge changes from Martin Hunt:
+
+ * d30v-opc.c: Change mvfacc to accept 6-bit unsigned values.
+
+ * d30v-opc.c (pre_defined_registers): Add control registers from 0-63.
+ (d30v_opcode_tabel): Add dbt, rtd, srah, and srlh instructions. Fix
+ rot2h, sra2h, and srl2h to use new SHORT_A5S format.
+
+ * d30v-dis.c (print_insn): Fix disassembly of SHORT_D2 opcodes.
+
+ * d30v-dis.c (print_insn): First operand of d*i (delayed
+ branch) instructions is relative.
+
+ * d30v-opc.c (d30v_opcode_table): Change form for repeati.
+ (d30v_operand_table): Add IMM6S3 type.
+ (d30v_format_table): Change SHORT_D2. Add LONG_Db.
+
+ * d30v-dis.c: Fix bug with ".s" and ".l" extensions
+ and cmp instructions.
+
+ * d30v-opc.c: Correct entries for repeat*, and sat*.
+ Make IMM5 unsigned. Create IMM6U and IMM12S3U operand
+ types. Correct several formats.
+
+ * d30v-opc.c: (pre_defined_registers): Add dpsw and dpc.
+
+ * d30v-opc.c (pre_defined_registers): Change control registers.
+
+ * d30v-opc.c (d30v_format_table): Correct SHORT_C1 and
+ SHORT_C2. Manual was incorrect.
+
+ * d30v-dis.c (lookup_opcode): Return value now indicates
+ if an opcode has a short and a long form. Used for deciding
+ to append a ".s" or ".l".
+ (print_insn): Append a ".s" to an instruction if it is
+ the short form and ".l" if it is a long form. Do not append
+ anything if the instruction has only one possible size.
+
+ * d30v-opc.c: Change mulx2h to require an even register.
+ New form: SHORT_A2; a SHORT_A form that needs an even
+ register as the first operand.
+
+ * d30v-dis.c (print_insn_d30v): Fix problem where the last
+ instruction was not being disassembled if there were an odd
+ number of instructions.
+
+ * d30v-opc.c (SHORT_M2, LONG_M2): Two new forms.
+
+end-sanitize-d30v
+start-sanitize-v850e
+Fri Sep 12 11:43:54 1997 Nick Clifton <nickc@cygnus.com>
+
+ * v850-dis.c (disassemble): Improved display of register lists.
+
+end-sanitize-v850e
+Thu Sep 11 17:35:10 1997 Doug Evans <dje@canuck.cygnus.com>
+
+ * sparc-opc.c (sparc_opcodes): Fix assembler args to
+ fzeros, fones, fsrc1, fsrc1s, fsrc2s, fnot1, fnot1s, fnot2s,
+ fors, fnors, fands, fnands, fxors, fxnors, fornot1s, fornot2s,
+ fandnot1s, fandnot2s.
+
+Tue Sep 9 10:03:49 1997 Doug Evans <dje@canuck.cygnus.com>
+
+ * sparc-opc.c (sparc_opcodes): Fix op3 field for fcmpq/fcmpeq.
+
+Mon Sep 8 14:06:59 1997 Doug Evans <dje@canuck.cygnus.com>
+
+ * cgen-asm.c (cgen_parse_address): New argument resultp.
+ All callers updated.
+ * m32r-asm.c (parse_h_hi16): Right shift numbers by 16.
+
+Tue Sep 2 18:39:08 1997 Jeffrey A Law (law@cygnus.com)
+
+ * mn10200-dis.c (disassemble): PC relative instructions are
+ relative to the next instruction, not the current instruction.
+
+Tue Sep 2 15:41:55 1997 Nick Clifton <nickc@cygnus.com>
+
+ * v850-dis.c (disassemble): Only signed extend values that are not
+ returned by extract functions.
+ Remove use of V850_OPERAND_ADJUST_SHORT_MEMORY flag.
+
+Tue Sep 2 15:39:40 1997 Nick Clifton <nickc@cygnus.com>
+
+ * v850-opc.c: Update comments. Remove use of
+ V850_OPERAND_ADJUST_SHORT_MEMORY. Fix several operand patterns.
+
+Tue Aug 26 09:42:28 1997 Nick Clifton <nickc@cygnus.com>
+
+ * v850-opc.c (MOVHI): Immediate parameter is unsigned.
+
+Mon Aug 25 15:58:07 1997 Christopher Provenzano <proven@cygnus.com>
+
+ * configure: Rebuilt with latest devo autoconf for NT support.
+
+Fri Aug 22 10:35:15 1997 Nick Clifton <nickc@cygnus.com>
+
+ * v850-dis.c (disassemble): Use curly brace syntax for register
+ lists.
+
+ * v850-opc.c (v850_opcodes[]): Add NOT_R0 flag to decect cases
+ where r0 is being used as a destination register.
+
+start-sanitize-v850e
+Thu Aug 21 11:09:09 1997 Nick Clifton <nickc@cygnus.com>
+
+ * v850-opc.c (v850_opcodes[]): Move divh opcodes next to each other.
+end-sanitize-v850e
+
+start-sanitize-sh4
+Wed Aug 20 00:43:11 1997 J"orn Rennecke <amylaar@cygnus.co.uk>
+
+ * sh-opc.h (sh_arg_type): Add A_SGR and A_DBR.
+ (sh_nibble_type, sh_arg_type): Add SH4 floating point extensions.
+ (sh_table): Likewise. Add movca.l, ocbi, ocbp, ocbwb.
+ Add insns to access SGR and DBR.
+ * sh-dis.c (print_insn_shx): Add SH4 floating point extensions.
+
+end-sanitize-sh4
+Tue Aug 19 10:59:59 1997 Richard Henderson <rth@cygnus.com>
+
+ * alpha-opc.c (alpha_opcodes): Fix hw_rei_stall mungage.
+
+start-sanitize-v850e
+Mon Aug 18 11:10:03 1997 Nick Clifton <nickc@cygnus.com>
+
+ * v850-opc.c (v850_opcodes[]): Remove use of flag field.
+ * v850-opc.c (v850_opcodes[]): Add support for reversed short load
+ opcodes..
+
+Mon Aug 18 11:08:25 1997 Nick Clifton <nickc@cygnus.com>
+
+ * configure (cgen_files): Add support for v850e target.
+ * configure.in (cgen_files): Add support for v850e target.
+
+Mon Aug 18 11:08:25 1997 Nick Clifton <nickc@cygnus.com>
+
+ * configure (cgen_files): Add support for v850ea target.
+ * configure.in (cgen_files): Add support for v850ea target.
+end-sanitize-v850e
+
+Fri Aug 15 05:17:48 1997 Doug Evans <dje@canuck.cygnus.com>
+
+ * configure.in (bfd_arc_arch): Add.
+ * configure: Rebuild.
+ * Makefile.am (ALL_MACHINES): Add arc-dis.lo, arc-opc.lo.
+ * Makefile.in: Rebuild.
+ * arc-dis.c, arc-opc.c: New files.
+ * disassemble.c (ARCH_all): Define ARCH_arc.
+ (disassembler): Add ARC support.
+
+Wed Aug 13 18:52:11 1997 Nick Clifton <nickc@cygnus.com>
+
+start-sanitize-v850e
+ * v850-dis.c (disassemble): Add support for v850EA instructions.
+
+ * v850-opc.c (insert_i5div, extract_i5div): New Functions.
+ (v850_opcodes): Add v850EA instructions.
+
+ * v850-dis.c (disassemble): Add support for v850E instructions.
+
+ * v850-opc.c (insert_d5_4, extract_d5_4, insert_d16_16,
+ extract_d16_16, insert_i9, extract_i9, insert_u9, extract_u9,
+ insert_spe, extract_spe): New Functions.
+ (v850_opcodes): Add v850E instructions.
+end-sanitize-v850e
+
+ * v850-opc.c: Reorganised and re-layed out to improve readability
+ and portability.
+
+Tue Aug 5 23:09:31 1997 Ian Lance Taylor <ian@cygnus.com>
+
+ * configure: Rebuild with autoconf 2.12.1.
+
+Mon Aug 4 12:02:16 1997 Ian Lance Taylor <ian@cygnus.com>
+
+ * aclocal.m4, configure: Rebuild with new automake patches.
+
+Fri Aug 1 13:02:04 1997 Ian Lance Taylor <ian@cygnus.com>
+
+ * configure.in: Set enable_shared before AM_PROG_LIBTOOL.
+ * acinclude.m4: Just include acinclude.m4 from BFD.
+ * aclocal.m4, configure: Rebuild.
+
+Thu Jul 31 21:44:42 1997 Ian Lance Taylor <ian@cygnus.com>
+
+ * Makefile.am: New file, based on old Makefile.in.
+ * acconfig.h: New file.
+ * acinclude.m4: New file.
+ * stamp-h.in: New file.
+ * configure.in: Call AM_INIT_AUTOMAKE and AM_PROG_LIBTOOL.
+ Removed shared library handling; now handled by libtool. Replace
+ AC_CONFIG_HEADER with AM_CONFIG_HEADER. Call AM_MAINTAINER_MODE,
+ AM_CYGWIN32, and AM_EXEEXT. Replace AC_PROG_INSTALL with
+ AM_PROG_INSTALL. Change all .o files to .lo. Remove stamp-h
+ handling in AC_OUTPUT.
+ * dep-in.sed: Change .o to .lo.
+ * Makefile.in: Now built with automake.
+ * aclocal.m4: Now built with aclocal.
+ * config.in, configure: Rebuild.
+
+Mon Jul 28 21:52:24 1997 Jeffrey A Law (law@cygnus.com)
+
+ * mips-opc.c: Fix typo/thinko in "eret" instruction.
+
+start-sanitize-r5900
+Mon Jul 28 22:07:14 1997 Andrew Cagney <cagney@b1.cygnus.com>
+
+ * mips-opc.c: Fix coding of mtsa.
+
+end-sanitize-r5900
+Thu Jul 24 13:03:26 1997 Doug Evans <dje@canuck.cygnus.com>
+
+ * sparc-opc.c (sparc_opcodes): Fix spelling on fpaddX, fpsubX insns.
+ Make array const.
+ * sparc-dis.c (sorted_opcodes): New static local.
+ (struct opcode_hash): `opcode' is pointer to const element.
+ (build_hash): First arg is now table of sorted pointers.
+ (print_insn_sparc): Sort opcodes by sorting table of pointers.
+ (compare_opcodes): Update.
+
+Tue Jul 15 12:05:23 1997 Doug Evans <dje@canuck.cygnus.com>
+
+ * cgen-opc.c: #include <ctype.h>.
+ (hash_keyword_name): New arg `case_sensitive_p'. Callers updated.
+ Handle case insensitive hashing.
+ (hash_keyword_value): Change type of `value' to unsigned int.
+
+Thu Jul 10 12:56:10 1997 Jeffrey A Law (law@cygnus.com)
+
+ * mips-opc.c (mips_builtin_opcodes): If an insn uses single
+ precision FP, mark it as such. Likewise for double precision
+ FP. Mark ISA1 insns. Consolidate duplicate opcodes where
+ possible.
+start-sanitize-r5900
+ (mips_builtin_opcodes): Remove non-existant r5900 instructions
+end-sanitize-r5900
+
+start-sanitize-r5900
+Thu Jun 26 16:20:27 1997 Jeffrey A Law (law@cygnus.com)
+
+ * mips-opc.c (mips_builtin_opcodes): Add "pinteh", "pexeh" and
+ "pexew" as synonyms for "pintoh", "pexoh", "pexow".
+
+end-sanitize-r5900
+Wed Jun 25 15:25:57 1997 Felix Lee <flee@cirdan.cygnus.com>
+
+ * ppc-opc.c (extract_nsi): make unsigned expression signed before
+ negating it.
+ (UNUSED): remove one level of parens, so MSVC doesn't choke on
+ nesting depth when all the macros are expanded.
+
+Tue Jun 17 17:02:17 1997 Ian Lance Taylor <ian@cygnus.com>
+
+ * sparc-opc.c: The fcmp v9a instructions take an integer register
+ as a destination, not a floating point register. From Christian
+ Kuehnke <Christian.Kuehnke@arbi.Informatik.Uni-Oldenburg.DE>.
+
+Mon Jun 16 14:13:18 1997 Ian Lance Taylor <ian@cygnus.com>
+
+ * m68k-dis.c (print_insn_arg): Print case 7.2 using %pc@()
+ syntax. From Roman Hodek
+ <rnhodek@faui22c.informatik.uni-erlangen.de>.
+
+ * i386-dis.c (twobyte_has_modrm): Fix pand.
+
+Mon Jun 16 14:08:38 1997 Michael Taylor <mbt@mit.edu>
+
+ * i386-dis.c (dis386_twobyte): Fix pand and pandn.
+
+Tue Jun 10 11:26:47 1997 H.J. Lu <hjl@gnu.ai.mit.edu>
+
+ * arm-dis.c: Add prototypes for arm_decode_shift and
+ print_insn_arm.
+
+Mon Jun 2 11:39:04 1997 Gavin Koch <gavin@cygnus.com>
+
+ * mips-opc.c: Add r3900 insns.
+
+Tue May 27 15:55:44 1997 Ian Lance Taylor <ian@cygnus.com>
+
+ * sh-dis.c (print_insn_shx): Change relmask to bfd_vma. Don't
+ print delay slot instructions on the same line. When using a PC
+ relative load, add a comment with the value being loaded if it can
+ be obtained.
+
+Tue May 27 11:02:08 1997 Alan Modra <alan@spri.levels.unisa.edu.au>
+
+ * i386-dis.c (dis386[], dis386_twobyte[]): change pushl/popl
+ to pushS/popS for segment regs and byte constant so that
+ pushw/popw printed when in 16 bit data mode.
+
+ * i386-dis.c (dis386[]): change cwtl, cltd to cWtS, cStd to
+ print cbtw, cwtd in 16 bit data mode.
+ * i386-dis.c (putop): extra case W to support above.
+
+ * i386-dis.c (print_insn_x86): print addr32 prefix when given
+ address size prefix in 16 bit address mode.
+
+Fri May 23 16:47:23 1997 Ian Lance Taylor <ian@cygnus.com>
+
+ * sh-dis.c: Reindent. Rename local variable fprintf to
+ fprintf_fn.
+
+Thu May 22 14:06:02 1997 Doug Evans <dje@canuck.cygnus.com>
+
+ * m32r-opc.c (m32r_cgen_insn_table, cmpui): Undo patch of May 2.
+
+Tue May 20 11:26:27 1997 Gavin Koch <gavin@cygnus.com>
+
+ * mips-opc.c (mips_builtin_opcodes): Moved INSN_ISA field into new
+ field membership.
+ * mips16-opc.c (mip16_opcodes): same.
+
+Mon May 12 15:10:53 1997 Jim Wilson <wilson@cygnus.com>
+
+ * m68k-opc.c (moveb): Change $d to %d.
+
+Mon May 5 14:28:41 1997 Ian Lance Taylor <ian@cygnus.com>
+
+ * i386-dis.c: (dis386_twobyte): Add MMX instructions.
+ (twobyte_has_modrm): Likewise.
+ (grps): Likewise.
+ (OP_MMX, OP_EM, OP_MS): New static functions.
+
+ * i386-dis.c: Revert patch of April 4. The output now matches
+ what gcc generates.
+
+Fri May 2 12:48:37 1997 Doug Evans <dje@canuck.cygnus.com>
+
+ * m32r-opc.c (m32r_cgen_insn_table, cmpui): Use $uimm16 instead
+ of $simm16.
+
+Thu May 1 15:34:15 1997 Doug Evans <dje@canuck.cygnus.com>
+
+ * m32r-opc.h (CGEN_ARCH): Renamed from CGEN_CPU.
+
+Tue Apr 15 12:40:08 1997 Ian Lance Taylor <ian@cygnus.com>
+
+ * Makefile.in (install): Depend upon installdirs.
+ (installdirs): New target.
+
+Mon Apr 14 12:13:51 1997 Ian Lance Taylor <ian@cygnus.com>
+
+ From Thomas Graichen <graichen@rzpd.de>:
+ * configure.in: Use ${CONFIG_SHELL} when running $ac_config_sub.
+ * configure: Rebuild.
+
+Sun Apr 13 17:50:41 1997 Doug Evans <dje@canuck.cygnus.com>
+
+ * cgen-*.c, m32r-*.c: #include sysdep.h instead of config.h.
+ Delete string{,s}.h support.
+
+Thu Apr 10 14:44:56 1997 Doug Evans <dje@canuck.cygnus.com>
+
+ * cgen-asm.c (cgen_parse_operand_fn): New global.
+ (cgen_parse_{{,un}signed_integer,address}): Update call to
+ cgen_parse_operand_fn.
+ (cgen_init_parse_operand): New function.
+ * m32r-asm.c (parse_insn_normal): cgen_init_parse_operand renamed
+ from cgen_asm_init_parse.
+ (m32r_cgen_assemble_insn): New operand `errmsg'.
+ Delete call to as_bad, return error message to caller.
+ (m32r_cgen_asm_hash_keywords): #if 0 out.
+
+Wed Apr 9 12:05:25 1997 Andreas Schwab <schwab@issan.informatik.uni-dortmund.de>
+
+ * m68k-dis.c (print_insn_arg) [case 'd']: Print as address register,
+ not data register.
+ [case 'J']: Fix typo in register name.
+
+Mon Apr 7 16:48:22 1997 Ian Lance Taylor <ian@cygnus.com>
+
+ * configure.in: Substitute SHLIB_LIBS.
+ * configure: Rebuild.
+ * Makefile.in (SHLIB_LIBS): New variable.
+ ($(SHLIB)): Use $(SHLIB_LIBS).
+
+Mon Apr 7 11:45:44 1997 Doug Evans <dje@canuck.cygnus.com>
+
+ * cgen-dis.c (build_dis_hash_table): Fix xmalloc size computation.
+
+ * cgen-opc.c (hash_keyword_name): Improve algorithm.
+
+ * disassemble.c (disassembler): Handle m32r.
+
+Fri Apr 4 12:29:38 1997 Doug Evans <dje@canuck.cygnus.com>
+
+ * m32r-asm.c, m32r-dis.c, m32r-opc.c, m32r-opc.h: New files.
+ * cgen-asm.c, cgen-dis.c, cgen-opc.c: New files.
+ * Makefile.in (CFILES): Add them.
+ (ALL_MACHINES): Add them.
+ (dependencies): Regenerate.
+ * configure.in (cgen_files): New variable.
+ (bfd_m32r_arch): Add entry.
+ * configure: Regenerate.
+
+Fri Apr 4 14:04:16 1997 Ian Lance Taylor <ian@cygnus.com>
+
+ * configure.in: Correct file names for bfd_mn10[23]00_arch.
+ * configure: Rebuild.
+
+ * Makefile.in: Rebuild dependencies.
+
+ * d10v-dis.c: Include "ansidecl.h" before "opcode/d10v.h".
+
+ * i386-dis.c (float_reg): Swap fsubrp and fsubp. Swap fdivrp and
+ fdivp.
+
+Thu Apr 3 13:22:45 1997 Ian Lance Taylor <ian@cygnus.com>
+
+ * Branched binutils 2.8.
+
+Wed Apr 2 12:23:53 1997 Ian Lance Taylor <ian@cygnus.com>
+
+ * m10200-dis.c: Rename from mn10200-dis.c.
+ * m10200-opc.c: Rename from mn10200-opc.c.
+ * m10300-dis.c: Rename from mn10300-dis.c
+ * m10300-opc.c: Rename from mn10300-opc.c.
+ * Makefile.in: Update accordingly.
+
+ * mips16-opc.c: Add mul and dmul macros.
+
+Tue Apr 1 16:27:45 1997 Klaus Kaempf <kkaempf@progis.de>
+
+ * makefile.vms: Update CFLAGS, add clean target.
+
+Fri Mar 28 12:10:09 1997 Ian Lance Taylor <ian@cygnus.com>
+
+ * mips-opc.c: Add "wait". From Ralf Baechle
+ <ralf@gnu.ai.mit.edu>.
+
+ * configure.in: Add stdlib.h to AC_CHECK_HEADERS list.
+ * configure, config.in: Rebuild.
+ * sysdep.h: Include <stdlib.h> if it exists.
+ * sparc-dis.c: Include <stdio.h> and "sysdep.h". Don't include
+ <string.h>.
+ * Makefile.in: Rebuild dependencies.
+
+Thu Mar 27 14:24:43 1997 Ian Lance Taylor <ian@cygnus.com>
+
+ * ppc-opc.c: Add PPC 403 instructions and extended opcodes. From
+ Andrew Bray <andy@madhouse.demon.co.uk>.
+
+ * mips-opc.c: Add cast when setting mips_opcodes.
+
+Tue Mar 25 23:04:00 1997 Stu Grossman (grossman@critters.cygnus.com)
+
+ * v850-dis.c (disassemble): Fix sign extension problem.
+ * v850-opc.c (extract_d*): Fix sign extension problems to make
+ disassembly calculate branch offsets correctly.
+
+Mon Mar 24 13:22:13 1997 Ian Lance Taylor <ian@cygnus.com>
+
+ * sh-opc.h: Add bf/s and bt/s as synonyms for bf.s and bt.s.
+
+ * mips-opc.c: Add dctr and dctw.
+
+start-sanitize-d30v
+Sun Mar 23 18:08:10 1997 Martin M. Hunt <hunt@pizza.cygnus.com>
+
+ * d30v-dis.c (print_insn): Change the way signed constants
+ are displayed.
+end-sanitize-d30v
+Fri Mar 21 14:37:52 1997 Ian Lance Taylor <ian@cygnus.com>
+
+ * Makefile.in (BFD_H): New variable.
+ (HFILES): New variable.
+ (CFILES): Add all C files.
+ (.dep, .dep1, dep.sed, dep, dep-in): New targets.
+ Delete old dependencies, and build new ones.
+ * dep-in.sed: New file.
+
+Thu Mar 20 19:03:30 1997 Philippe De Muyter <phdm@info.ucl.ac.be>
+
+ * m68k-opc.c (m68k_opcode_aliases): Added blo and blo{s,b,w,l}.
+
+start-sanitize-coldfire
+Wed Mar 19 06:53:58 1997 J.T. Conklin <jtc@rtl.cygnus.com>
+
+ * m68k-opc.c (m68k_opcodes): Provide coldfire division module
+ instructions.
+
+end-sanitize-coldfire
+Tue Mar 18 14:17:03 1997 Jeffrey A Law (law@cygnus.com)
+
+ * mn10200-opc.c: Change "trap" to "syscall".
+ * mn10300-opc.c: Add new "syscall" instruction.
+
+Mon Mar 17 08:48:03 1997 J.T. Conklin <jtc@beauty.cygnus.com>
+
+ * m68k-opc.c (m68k_opcodes): Provide correct entries for mulsl and
+ mulul insns on the coldfire.
+
+Sat Mar 15 17:13:05 1997 Ian Lance Taylor <ian@cygnus.com>
+
+ * arm-dis.c (print_insn_arm): Don't print instruction bytes.
+ (print_insn_big_arm): Set bytes_per_chunk and display_endian.
+ (print_insn_little_arm): Likewise.
+
+Fri Mar 14 15:08:59 1997 Ian Lance Taylor <ian@cygnus.com>
+
+ Based on patches from H.J. Lu <hjl@lucon.org>:
+ * i386-dis.c (fetch_data): Add prototype.
+ * m68k-dis.c (fetch_data): Add prototype.
+ (dummy_print_address): Add prototype. Make static.
+ * ppc-opc.c (valid_bo): Add prototype.
+ * sparc-dis.c (build_hash_table): Add prototype.
+ (is_delayed_branch, compute_arch_mask): Add prototypes.
+ (print_insn_sparc): Make several local variables const.
+ (compare_opcodes): Change arguments to const PTR. Add prototype.
+ * sparc-opc.c (arg): Change name field to be const.
+ (lookup_name, lookup_value): Add prototypes. Change table and
+ name parameters to be const.
+ (sparc_encode_asi): Change name parameter to be const.
+ (sparc_encode_membar, sparc_encode_prefetch): Likewise.
+ (sparc_encode_sparclet_cpreg): Likewise.
+ (sparc_decode_asi): Change return type to be const.
+ (sparc_decode_membar, sparc_decode_prefetch): Likewise.
+ (sparc_decode_sparclet_cpreg): Likewise.
+
+Fri Mar 7 10:51:49 1997 Ian Lance Taylor <ian@cygnus.com>
+
+ * Makefile.in ($(SHLINK)): Just use ln -s, not ln -sf, since
+ Solaris doesn't like the combined options, and the -f is
+ unnecessary.
+ (stamp-tshlink, install): Likewise.
+
+Thu Mar 6 16:51:11 1997 Jeffrey A Law (law@cygnus.com)
+
+ * mn10300-opc.c (IMM16_PCREL, SD8N_PCREL, D16_SHIFT): Mark these
+ as relaxable.
+
+Tue Mar 4 06:10:36 1997 J.T. Conklin <jtc@cygnus.com>
+
+ * m68k-opc.c (m68k_opcodes): Fix last change for the mc68010.
+
+Mon Mar 3 07:45:20 1997 J.T. Conklin <jtc@cygnus.com>
+
+ * m68k-opc.c (m68k_opcodes): Added entries for the tst insns on
+ the mc68000.
+
+Thu Feb 27 14:04:32 1997 Philippe De Muyter <phdm@info.ucl.ac.be>
+
+ * m68k-opc.c (m68k_opcodes): Added swbegl pseudo-instruction.
+
+start-sanitize-tic80
+Thu Feb 27 11:36:41 1997 Michael Meissner <meissner@cygnus.com>
+
+ * tic80-dis.c (print_insn_tic80): Set info->bytes_per_line to 8.
+
+Wed Feb 26 15:34:48 1997 Michael Meissner <meissner@cygnus.com>
+
+ * tic80-opc.c (tic80_predefined_symbols): Define r25 properly.
+
+end-sanitize-tic80
+Wed Feb 26 13:38:30 1997 Andreas Schwab <schwab@issan.informatik.uni-dortmund.de>
+
+ * m68k-dis.c (NEXTSINGLE, NEXTDOUBLE, NEXTEXTEND): Use
+ floatformat_to_double to make portable.
+ (print_insn_arg): Use NEXTEXTEND macro when extracting extended
+ precision float.
+
+Mon Feb 24 19:26:12 1997 Dawn Perchik <dawn@cygnus.com>
+
+ * mips-opc.c: Initialize mips_opcodes to mips_builtin_opcodes,
+ and bfd_mips_num_opcodes to bfd_mips_num_builtin_opcodes.
+
+Mon Feb 24 15:19:01 1997 Martin M. Hunt <hunt@pizza.cygnus.com>
+
+ * d10v-dis.c, d10v-opc.c: Change pre_defined_registers to
+ d10v_predefined_registers and reg_name_cnt to d10v_reg_name_cnt.
+
+start-sanitize-tic80
+Mon Feb 24 14:33:26 1997 Fred Fish <fnf@cygnus.com>
+
+ * tic80-opc.c (LSI_SCALED): Renamed from this ...
+ (OFF_SL_BR_SCALED): ... to this, and added the flag
+ TIC80_OPERAND_BASEREL to the flags word.
+ (tic80_opcodes): Replace all occurances of LSI_SCALED with
+ OFF_SL_BR_SCALED.
+
+end-sanitize-tic80
+Sat Feb 22 21:25:00 1997 Dawn Perchik <dawn@cygnus.com>
+
+ * mips-opc.c: Add macros for cop0, cop1 cop2 and cop3.
+ Change mips_opcodes from const array to a pointer,
+ and change bfd_mips_num_opcodes from const int to int,
+ so that we can increase the size of the mips opcodes table
+ dynamically.
+
+start-sanitize-tic80
+Sat Feb 22 21:03:47 1997 Fred Fish <fnf@cygnus.com>
+
+ * tic80-opc.c (tic80_predefined_symbols): Revert change to
+ store BITNUM values in the table in one's complement form
+ to match behavior when assembler is given a raw numeric
+ value for a BITNUM operand.
+ * tic80-dis.c (print_operand_bitnum): Ditto.
+
+end-sanitize-tic80
+start-sanitize-d30v
+Fri Feb 21 16:31:18 1997 Martin M. Hunt <hunt@pizza.cygnus.com>
+
+ * d30v-opc.c: Removed references to FLAG_X.
+
+end-sanitize-d30v
+Wed Feb 19 14:51:20 1997 Ian Lance Taylor <ian@cygnus.com>
+
+ * Makefile.in: Add dependencies on ../bfd/bfd.h as required.
+
+start-sanitize-d30v
+Tue Feb 18 17:43:43 1997 Martin M. Hunt <hunt@pizza.cygnus.com>
+
+ * Makefile.in: Added d30v object files.
+ * configure: (bfd_d30v_arch) Rebuilt.
+ * configure.in: (bfd_d30v_arch) Added new case.
+ * d30v-dis.c: New file.
+ * d30v-opc.c: New file.
+ * disassemble.c (disassembler) Add entry for d30v.
+
+end-sanitize-d30v
+start-sanitize-tic80
+Tue Feb 18 16:32:08 1997 Fred Fish <fnf@cygnus.com>
+
+ * tic80-opc.c (tic80_predefined_symbols): Add symbolic
+ representations for the floating point BITNUM values.
+
+Fri Feb 14 12:14:05 1997 Fred Fish <fnf@cygnus.com>
+
+ * tic80-opc.c (tic80_predefined_symbols): Store BITNUM values
+ in the table in one's complement form, as they appear in the
+ actual instruction.
+ (tic80_symbol_to_value): Use macros to access predefined
+ symbol fields.
+ (tic80_value_to_symbol): Ditto.
+ (tic80_next_predefined_symbol): New function.
+ * tic80-dis.c (print_operand_bitnum): Remove code that did
+ one's complement for BITNUM values.
+
+end-sanitize-tic80
+start-sanitize-r5900
+Fri Feb 14 13:56:51 1997 Gavin Koch <gavin@cygnus.com>
+
+ * mips-opc.c: bug fix, can't mark insns INSN_5900 and INSN_ISA4
+
+end-sanitize-r5900
+Thu Feb 13 21:56:51 1997 Klaus Kaempf <kkaempf@progis.de>
+
+ * makefile.vms: Remove 8 bit characters. Update to latest
+ gcc release.
+
+Thu Feb 13 20:41:22 1997 Philippe De Muyter <phdm@info.ucl.ac.be>
+
+ * m68k-opc.c (m68k_opcodes): Add swbeg pseudo-instruction.
+
+Thu Feb 13 16:30:02 1997 Jeffrey A Law (law@cygnus.com)
+
+ * mn10200-opc.c (IMM16_PCREL): This is a signed operand.
+ (IMM24_PCREL): Likewise.
+
+Thu Feb 13 13:28:43 1997 Ian Lance Taylor <ian@cygnus.com>
+
+ * mips-dis.c (print_mips16_insn_arg): Use memaddr - 2 as the base
+ address for an extended PC relative instruction that is not a
+ branch.
+
+Wed Feb 12 12:27:40 1997 Andreas Schwab <schwab@issan.informatik.uni-dortmund.de>
+
+ * m68k-dis.c (print_insn_m68k): Set bytes_per_chunk and
+ bytes_per_line.
+
+start-sanitize-tic80
+Tue Feb 11 16:36:31 1997 Fred Fish <fnf@cygnus.com>
+
+ * tic80-opc.c (tic80_operands): Fix typo '+' -> '|'.
+ (tic80_opcodes): Sort entries so that long immediate forms
+ come after short immediate forms, making it easier for
+ assembler to select the right one for a given operand.
+
+end-sanitize-tic80
+Tue Feb 11 15:26:47 1997 Ian Lance Taylor <ian@cygnus.com>
+
+ * mips-dis.c (_print_insn_mips): Set bytes_per_chunk and
+ display_endian.
+ (print_insn_mips16): Likewise.
+
+start-sanitize-r5900
+Fri Feb 7 11:12:44 1997 Gavin Koch <gavin@cygnus.com>
+
+ * mips-opc.c: add r5900.
+
+end-sanitize-r5900
+start-sanitize-tic80
+Mon Feb 10 10:12:41 1997 Fred Fish <fnf@cygnus.com>
+
+ * tic80-opc.c (tic80_symbol_to_value): Changed to accept
+ a symbol class that restricts translation to just that
+ class (general register, condition code, etc).
+
+Thu Feb 6 17:34:09 1997 Fred Fish <fnf@cygnus.com>
+
+ * tic80-opc.c (tic80_operands): Add REG_0_E, REG_22_E,
+ and REG_DEST_E for register operands that have to be
+ an even numbered register. Add REG_FPA for operands that
+ are one of the floating point accumulator registers.
+ Add TIC80_OPERAND_MASK to flags for ENDMASK operand.
+ (tic80_opcodes): Change entries that need even numbered
+ register operands to use the new operand table entries.
+ Add "or" entries that are identical to "or.tt" entries.
+
+end-sanitize-tic80
+Wed Feb 5 11:12:44 1997 Ian Lance Taylor <ian@cygnus.com>
+
+ * mips16-opc.c: Add new cases of exit instruction for
+ disassembler.
+ * mips-dis.c (print_mips16_insn_arg): Display floating point
+ registers in operands of exit instruction. Print `$' before
+ register names in operands of entry and exit instructions.
+
+start-sanitize-tic80
+Thu Jan 30 14:09:03 1997 Fred Fish <fnf@cygnus.com>
+
+ * tic80-opc.c (tic80_predefined_symbols): Table of name/value
+ pairs for all predefined symbols recognized by the assembler.
+ Also used by the disassembling routines.
+ (tic80_symbol_to_value): New function.
+ (tic80_value_to_symbol): New function.
+ * tic80-dis.c (print_operand_control_register,
+ print_operand_condition_code, print_operand_bitnum):
+ Remove private tables and use tic80_value_to_symbol function.
+
+end-sanitize-tic80
+Thu Jan 30 11:30:45 1997 Martin M. Hunt <hunt@pizza.cygnus.com>
+
+ * d10v-dis.c (print_operand): Change address printing
+ to correctly handle PC wrapping. Fixes PR11490.
+
+Wed Jan 29 09:39:17 1997 Jeffrey A Law (law@cygnus.com)
+
+ * mn10200-opc.c (mn10200_operands): Make 8 and 16 bit pc-relative
+ branches relaxable.
+
+Tue Jan 28 15:57:34 1997 Ian Lance Taylor <ian@cygnus.com>
+
+ * mips-dis.c (print_insn_mips16): Set insn_info information.
+ (print_mips16_insn_arg): Likewise.
+
+ * mips-dis.c (print_insn_mips16): Better handling of an extend
+ opcode followed by an instruction which can not be extended.
+
+Fri Jan 24 12:08:21 1997 J.T. Conklin <jtc@cygnus.com>
+
+ * m68k-opc.c (m68k_opcodes): Changed operand specifier for the
+ coldfire moveb instruction to not allow an address register as
+ destination. Although the documentation does not indicate that
+ this is invalid, experiments uncovered unexpected behavior.
+ Added a comment explaining the situation. Thanks to Andreas
+ Schwab for pointing this out to me.
+
+start-sanitize-tic80
+Wed Jan 22 20:13:51 1997 Fred Fish <fnf@cygnus.com>
+
+ * tic80-opc.c (tic80_opcodes): Expand comment to note that the
+ entries are presorted so that entries with the same mnemonic are
+ adjacent to each other in the table. Sort the entries for each
+ instruction so that this is true.
+
+end-sanitize-tic80
+Mon Jan 20 12:48:57 1997 Andreas Schwab <schwab@issan.informatik.uni-dortmund.de>
+
+ * m68k-dis.c: Include <libiberty.h>.
+ (print_insn_m68k): Sort the opcode table on the most significant
+ nibble of the opcode.
+
+start-sanitize-tic80
+Sat Jan 18 15:15:05 1997 Fred Fish <fnf@cygnus.com>
+
+ * tic80-dis.c (tic80_opcodes): Add "wrcr", "vmpy", "vrnd",
+ "vsub", "vst", "xnor", and "xor" instructions.
+ (V_a1): Renamed from V_a, msb of accumulator reg number.
+ (V_a0): Add macro, lsb of accumulator reg number.
+
+Fri Jan 17 18:24:31 1997 Fred Fish <fnf@cygnus.com>
+
+ * tic80-dis.c (print_insn_tic80): Broke excessively long
+ function up into several smaller ones and arranged for
+ the instruction printing function to be callable recursively
+ to print vector instructions that have both a load and a
+ math instruction packed into a single opcode.
+ * tic80-opc.c (tic80_opcodes): Expand comment for vld opcode
+ to explain why it comes after the other vector opcodes.
+
+end-sanitize-tic80
+Fri Jan 17 16:19:15 1997 J.T. Conklin <jtc@beauty.cygnus.com>
+
+ * m68k-opc.c (m68k_opcodes): add b, w, or l specifier to coldfire
+ move insns to handle immediate operands.
+
+Thu Jan 17 16:19:00 1997 Andreas Schwab <schwab@issan.informatik.uni-dortmund.de>
+
+ * m68k-opc.c (m68k_opcodes): Delete duplicate entry for "cmpil".
+ fix operand mask in the "moveml" entries for the coldfire.
+
+start-sanitize-tic80
+Thu Jan 16 20:54:40 1997 Fred Fish <fnf@cygnus.com>
+
+ * tic80-opc.c (V_a, V_m, V_S, V_Z, V_p, OP_V, MASK_V):
+ New macros for building vector instruction opcodes.
+ (tic80_opcodes): Remove all uses of FMT_SI, FMT_REG, and
+ FMT_LI, which were unused. The field is now a flags field.
+ Remove some opcodes that are possible, but illegal, such
+ as long immediate instructions with doubles for immediate
+ values. Add "vadd" and "vld" instructions.
+
+Wed Jan 15 18:59:51 1997 Fred Fish <fnf@cygnus.com>
+
+ * tic80-opc.c (tic80_operands): Reorder some table entries to make
+ the order more logical. Move the shift alias instructions ("rotl",
+ "shl", "ins", "rotr", "extu", "exts", "srl", and "sra" to be
+ interspersed with the regular sr.x and sl.x instructions. Add
+ and test new instruction opcodes for "sl", "sli", "sr", "sri", "st",
+ "sub", "subu", "swcr", and "trap".
+
+Tue Jan 14 19:42:50 1997 Fred Fish <fnf@cygnus.com>
+
+ * tic80-opc.c (OFF_SS_PC): Renamed from OFF_SS.
+ (OFF_SL_PC): Renamed from OFF_SL.
+ (OFF_SS_BR): New operand type for base relative operand.
+ (OFF_SL_BR): New operand type for base relative operand.
+ (REG_BASE): New operand type for base register operand.
+ (tic80_opcodes): Add and test "fmpy", "frndm", "frndn", "frndp",
+ "frndz", "fsqrt", "fsub", "illop0", "illopF", "ins", "jsr",
+ "ld", "ld.u", "lmo", "or", "rdcr", "rmo", "rotl", and "rotr"
+ instructions.
+ * tic80-dis.c (print_insn_tic80): Print opcode name with fixed width
+ 10 char field, padded with spaces on rhs, rather than a string
+ followed by a tab. Use renamed TIC80_OPERAND_PCREL flag bit rather
+ than old TIC80_OPERAND_RELATIVE. Add support for new
+ TIC80_OPERAND_BASEREL flag bit.
+
+Mon Jan 13 15:58:56 1997 Fred Fish <fnf@cygnus.com>
+
+ * tic80-dis.c (print_insn_tic80): Print floating point operands
+ as floats.
+ * tic80-opc.c (SPFI): Add single precision floating point
+ immediate operand type.
+ (ROTATE): Add rotate operand type for shifts.
+ (ENDMASK): Add for shifts.
+ (n): Macro for the 'n' bit.
+ (i): Macro for the 'i' bit.
+ (PD): Macro for the 'PD' field.
+ (P2): Macro for the 'P2' field.
+ (P1): Macro for the 'P1' field.
+ (tic80_opcodes): Add entries for "exts", "extu", "fadd",
+ "fcmp", and "fdiv".
+
+end-sanitize-tic80
+Mon Jan 6 15:06:55 1997 Jeffrey A Law (law@cygnus.com)
+
+ * mn10200-dis.c (disassemble): Mask off unwanted bits after
+ adding in current address for pc-relative operands.
+
+start-sanitize-tic80
+Mon Jan 6 10:56:25 1997 Fred Fish <fnf@cygnus.com>
+
+ * tic80-dis.c (R_SCALED): Add macro to test for ":s" modifier bit.
+ (print_insn_tic80): If R_SCALED then print ":s" modifier for operand.
+ * tic80-opc.c (REG0, REG22, REG27, SSOFF, LSOFF): Names
+ changed to REG_0, REG_22, REG_DEST, OFF_SS, OFF_SL respectively.
+ (SICR, LICR, REGM_SI, REGM_LI): Names changed to CR_SI, CR_LI,
+ REG_BASE_M_SI, REG_BASE_M_LI respectively.
+ (REG_SCALED, LSI_SCALED): New operand types.
+ (E): New macro for 'E' bit at bit 27.
+ (tic80_opcodes): Add and test dld, dld.u, dst, estop, and etrap
+ opcodes, including the various size flavors (b,h,w,d) for
+ the direct load and store instructions.
+
+Sun Jan 5 12:18:14 1997 Fred Fish <fnf@cygnus.com>
+
+ * tic80-dis.c (M_SI, M_LI): Add macros to test for ":m" modifier bit
+ in an instruction.
+ * tic80-dis.c (print_insn_tic80): Change comma and paren handling.
+ Use M_SI and M_LI macros to check for ":m" modifier for GPR operands.
+ * tic80-opc.c (tic80_operands): Add REGM_SI and REGM_LI operands.
+ (F, M_REG, M_LI, M_SI, SZ_REG, SZ_LI, SZ_SI, D, S): New bit-twiddlers.
+ (MASK_LI_M, MASK_SI_M, MASK_REG_M): Remove and replace in opcode
+ masks with "MASK_* & ~M_*" to get the M bit reset.
+ (tic80_opcodes): Add bsr, bsr.a, cmnd, cmp, dcachec, and dcachef.
+
+Sat Jan 4 19:05:05 1997 Fred Fish <fnf@cygnus.com>
+
+ * tic80-dis.c (print_insn_tic80): Print TIC80_OPERAND_RELATIVE
+ correctly. Add support for printing TIC80_OPERAND_BITNUM and
+ TIC80_OPERAND_CC, and TIC80_OPERAND_CR operands in symbolic
+ form.
+ * tic80-opc.c (tic80_operands): Add SSOFF, LSOFF, BITNUM,
+ CC, SICR, and LICR table entries.
+ (tic80_opcodes): Add and test "nop", "br", "bbo", "bbz",
+ "bcnd", and "brcr" opcodes.
+
+end-sanitize-tic80
+Fri Jan 3 18:32:11 1997 Fred Fish <fnf@cygnus.com>
+
+ * ppc-opc.c (powerpc_operands): Make comment match the
+ actual fields (no shift field).
+ * sparc-opc.c (sparc_opcodes): Document why this cannot be "const".
+start-sanitize-tic80
+ * tic80-dis.c (print_insn_tic80): Replace abort stub with a
+ partial implementation, work in progress.
+ * tic80-opc.c (tic80_operands): Begin construction operands table.
+ (tic80_opcodes): Continue populating opcodes table and start
+ filling in the operand indices.
+ (tic80_num_opcodes): Add this.
+end-sanitize-tic80
+
Fri Jan 3 12:13:52 1997 Ian Lance Taylor <ian@cygnus.com>
* m68k-opc.c: Add #B case for moveq.
* mn10300-dis.c (disassemble): Make sure all variables are initialized
before they are used.
-start-sanitize-v850
Tue Dec 31 12:20:38 1996 Jeffrey A Law (law@cygnus.com)
* v850-opc.c (v850_opcodes): Put curly-braces around operands
for "breakpoint" instruction.
-end-sanitize-v850
Tue Dec 31 15:38:13 1996 Ian Lance Taylor <ian@cygnus.com>
* Makefile.in (ALL_CFLAGS): Add -D_GNU_SOURCE.
(dep): Use ALL_CFLAGS rather than CFLAGS.
-start-sanitize-v850
Tue Dec 31 15:09:16 1996 Michael Meissner <meissner@tiktok.cygnus.com>
* v850-opc.c (D8_{6,7}): Set V850_OPERAND_ADJUST_SHORT_MEMORY
flag.
-end-sanitize-v850
Mon Dec 30 17:02:11 1996 Fred Fish <fnf@cygnus.com>
* Makefile.in (m68k-opc.o, alpha-opc.o): Remove dis-asm.h dependency.
* tic80-opc.c: Add file.
end-sanitize-tic80
-start-sanitize-d10v
Fri Dec 20 14:30:19 1996 Martin M. Hunt <hunt@pizza.cygnus.com>
* d10v-opc.c (pre_defined_registers): Add cr[0-15], dpc, dpsw, link.
-end-sanitize-d10v
Mon Dec 16 13:00:15 1996 Jeffrey A Law (law@cygnus.com)
* mn10200-opc.c (mn10200_operands): Add SIMM16N.
list.
(mn10300_opcodes): Use REGS for register list in "movm" instructions.
-start-sanitize-d10v
Mon Nov 18 15:20:35 1996 Michael Meissner <meissner@tiktok.cygnus.com>
* d10v-opc.c (d10v_opcodes): Add3 sets the carry.
-end-sanitize-d10v
Fri Nov 15 13:43:19 1996 Jeffrey A Law (law@cygnus.com)
* mn10300-opc.c (mn10300_opcodes): Demand parens around
the extended part of an instruction.
(mn10300_operands): Use new opcodes as appropriate.
-start-sanitize-d10v
Tue Nov 5 10:30:51 1996 Martin M. Hunt <hunt@pizza.cygnus.com>
* d10v-opc.c (d10v_opcodes): Declare the trap instruction
sequential so the assembler never parallelizes it with
other instructions.
-end-sanitize-d10v
Mon Nov 4 12:50:40 1996 Jeffrey A Law (law@cygnus.com)
* mn10300-opc.c (mn10300_operands): Add DN01 and AN01 for
(alpha_opcodes): Add new BWX, CIX, and MAX instructions.
Recategorize PALcode instructions.
-start-sanitize-v850
Wed Oct 30 16:46:58 1996 Jeffrey A Law (law@cygnus.com)
* v850-opc.c (v850_opcodes): Add relaxing "jbr".
-end-sanitize-v850
Tue Oct 29 16:30:28 1996 Ian Lance Taylor <ian@cygnus.com>
* mips-dis.c (_print_insn_mips): Don't print a trailing tab if
there are no operand types.
-start-sanitize-v850
Tue Oct 29 12:22:21 1996 Jeffrey A Law (law@cygnus.com)
* v850-opc.c (D9_RELAX): Renamed from D9, all references
changed.
(v850_operands): Make sure D22 immediately follows D9_RELAX.
-end-sanitize-v850
Fri Oct 25 12:12:53 1996 Ian Lance Taylor <ian@cygnus.com>
* i386-dis.c (print_insn_x86): Set info->bytes_per_line to 5.
-start-sanitize-v850
Thu Oct 24 17:53:52 1996 Jeffrey A Law (law@cygnus.com)
* v850-opc.c (insert_d8_6): Fix operand insertion for sld.w
* v850-opc.c (v850_opcodes): Add "jCC" instructions (aliases for
"bCC"instructions).
-end-sanitize-v850
Thu Oct 24 17:21:20 1996 Ian Lance Taylor <ian@cygnus.com>
* mips-dis.c (_print_insn_mips): Use a tab between the instruction
* mn10300-opc.c (mn10300_opcodes): Fix typo in opcode
field for movhu instruction.
-start-sanitize-v850
* v850-dis.c (disassemble): For V850_OPERAND_SIGNED operands,
cast value to "long" not "signed long" to keep hpux10
compiler quiet.
-end-sanitize-v850
Thu Oct 10 10:25:58 1996 Jeffrey A Law (law@cygnus.com)
* i386-dis.c (op_rtn): Change to be a pointer. Adjust uses
accordingly. Don't declare functions using op_rtn.
-start-sanitize-v850
Fri Sep 27 18:28:59 1996 Stu Grossman (grossman@critters.cygnus.com)
* v850-dis.c (disassemble): Add memaddr argument. Re-arrange
bit operands.
* (v850_opcodes): Add breakpoint insn.
-end-sanitize-v850
Mon Sep 23 12:32:26 1996 Ian Lance Taylor <ian@cygnus.com>
* m68k-opc.c: Move the fmovemx data register cases before the
* sparc-opc.c (sparc_opcodes): Add setuw, setsw, setx.
-start-sanitize-v850
Tue Sep 3 12:05:25 1996 Jeffrey A Law (law@cygnus.com)
* v850-dis.c (disassemble): Make static. Provide prototype.
(v850_opcodes): Fix mask for jarl and jr.
* v850-dis.c: New file. Skeleton for disassembler support.
- * Makefile.in Remove v850 references, they're not needed here
- and they weren't being sanitized away.
+ * Makefile.in Remove v850 references, they're not needed here.
* configure.in: Add v850-dis.o when building v850 toolchains.
* configure: Rebuilt.
* disassemble.c (disassembler): Call v850 disassembler.
* v850-opc.c (v850_opcodes): Add null opcode to mark the
end of the opcode table.
-end-sanitize-v850
-start-sanitize-d10v
Mon Aug 26 13:35:53 1996 Martin M. Hunt <hunt@pizza.cygnus.com>
* d10v-opc.c (pre_defined_registers): Added register pairs,
"r0-r1", "r2-r3", etc.
-end-sanitize-d10v
-start-sanitize-v850
Fri Aug 23 00:27:01 1996 Jeffrey A Law (law@cygnus.com)
* v850-opc.c (v850_operands): Make I16 be a signed operand.
* configure.in: (bfd_v850_arch) Add new case.
* v850-opc.c: New file.
-end-sanitize-v850
Mon Aug 19 15:21:38 1996 Doug Evans <dje@canuck.cygnus.com>
* sparc-dis.c (print_insn_sparc): Handle little endian sparcs.
-start-sanitize-d10v
Thu Aug 15 13:14:43 1996 Martin M. Hunt <hunt@pizza.cygnus.com>
* d10v-opc.c: Add additional information to the opcode
table to help determinine which instructions can be done
in parallel.
-end-sanitize-d10v
Thu Aug 15 13:11:13 1996 Stan Shebs <shebs@andros.cygnus.com>
* mpw-make.sed: Update editing of include pathnames to be
* alpha-opc.c (EV4EXTHWINDEX): Field width should be 8 not 5.
-start-sanitize-d10v
Mon Aug 12 14:30:37 1996 Martin M. Hunt <hunt@pizza.cygnus.com>
* d10v-opc.c (d10v_opcodes): Minor fixes to addi and bl.l.
* d10v-opc.c (d10v_opcodes): Correct 'mv' unit entry to EITHER.
-end-sanitize-d10v
Thu Aug 8 12:43:52 1996 Klaus Kaempf <kkaempf@progis.de>
* makefile.vms: Update for alpha-opc changes.
* i386-dis.c (print_insn_i386): Actually return the correct value.
(ONE, OP_ONE): #ifdef out; not used.
-start-sanitize-d10v
Fri Aug 2 17:47:03 1996 Martin M. Hunt <hunt@pizza.cygnus.com>
* d10v-opc.c (d10v_opcodes): Added 2 accumulator sub instructions.
Changed subi operand type to treat 0 as 16.
-end-sanitize-d10v
Wed Jul 31 16:21:41 1996 Ian Lance Taylor <ian@cygnus.com>
* m68k-opc.c: Add cpushl for the mcf5200. From Ken Rose
* arm-dis.c: (print_insn_arm): Provide decoding of the new
formats %h and %s.
-start-sanitize-d10v
Fri Jul 26 11:45:04 1996 Martin M. Hunt <hunt@pizza.cygnus.com>
* d10v-opc.c (d10v_operands): Added UNUM4S; a 4-bit accumulator shift.
(d10v_opcodes): Modified accumulator shift instructions to use UNUM4S.
-end-sanitize-d10v
Fri Jul 26 14:01:43 1996 Ian Lance Taylor <ian@cygnus.com>
* alpha-dis.c (print_insn_alpha_osf): Remove.
names based on info->flavour.
* disassemble.c: Always return print_insn_alpha for the alpha.
-start-sanitize-d10v
Thu Jul 25 15:24:17 1996 Martin M. Hunt <hunt@pizza.cygnus.com>
* d10v-dis.c (dis_long): Handle unknown opcodes.
* d10v-dis.c: Change all functions to use info->print_address_func.
-end-sanitize-d10v
Mon Jul 22 15:38:53 1996 Andreas Schwab <schwab@issan.informatik.uni-dortmund.de>
* m68k-opc.c (m68k_opcodes): Make opcode masks for the ColdFire
move ccr/sr insns more strict so that the disassembler only
selects them when the addressing mode is data register.
-start-sanitize-d10v
Mon Jul 22 11:25:24 1996 Martin M. Hunt <hunt@pizza.cygnus.com>
* d10v-opc.c (pre_defined_registers): Declare.
* d10v-dis.c (print_operand): Now uses pre_defined_registers
to pick a better name for the registers.
-end-sanitize-d10v
Mon Jul 22 13:47:23 1996 Ian Lance Taylor <ian@cygnus.com>
* sparc-opc.c: Fix opcode values for fpack16, and fpackfix. Fix
* configure: Rebuild.
* Makefile.in (install): Use @INSTALL_SHLIB@.
-start-sanitize-d10v
- Wed Jul 17 14:39:05 1996 Martin M. Hunt <hunt@pizza.cygnus.com>
+Wed Jul 17 14:39:05 1996 Martin M. Hunt <hunt@pizza.cygnus.com>
* configure: (bfd_d10v_arch) Add new case.
* configure.in: (bfd_d10v_arch) Add new case.
* d10v-opc.c: New file.
* disassemble.c (disassembler) Add entry for d10v.
-end-sanitize-d10v
Wed Jul 17 10:12:05 1996 J.T. Conklin <jtc@rtl.cygnus.com>
* m68k-opc.c (m68k_opcodes): Fix bugs in coldfire insns relating
shifted by 18, without any insertion or extraction function.
(insert_cr, extract_cr): Remove.
-start-sanitize-arc
-Mon Jul 3 11:54:31 1995 Ian Lance Taylor <ian@cygnus.com>
-
- * Makefile.in (ALL_MACHINES): Add arc-dis.o and arc-opc.o.
-
-end-sanitize-arc
Wed Jun 21 20:05:39 1995 Ken Raeburn <raeburn@cujo.cygnus.com>
* m68k-dis.c (print_insn_arg, print_indexed): Print "%" before
* disassemble.c (disassembler, case bfd_arch_arm): Disassemble for
the correct endianness.
-start-sanitize-arc
-Sat Apr 29 23:20:05 1995 Doug Evans <dje@chestnut.cygnus.com>
-
- * arc-opc.c (arc_opcodes): Add ARC_OPCODE_CONDITIONAL_BRANCH flag.
- (arc_suffixes): Use ARC_DELAY_{NONE,NORMAL,JUMP}.
-end-sanitize-arc
-
Mon Apr 24 14:18:05 1995 Jason Molenda (crash@phydeaux.cygnus.com>
* sh-opc.h (sh_nibble_type, sh_arg_type): remove trailing , from
* m68k-dis.c: Take out #define BREAK_UP_BIG_DECL kludge, because
gcc memory hog problem with initializer is fixed.
-start-sanitize-arc
-Wed Apr 12 09:04:12 1995 Doug Evans <dje@canuck.cygnus.com>
-
- * arc-opc.c (NULL): Define.
- (arc_operands, insn fields u,s): Delete.
- (arc_operands, insn fields a,b,c): Mark as signed.
- (arc_opcodes): No longer const, links computed at run-time.
- (arc_opcodes, mac/mul insns): Breakout suffixes as we don't handle
- suffixes that affect the insn code.
- (arc_opcodes): Resort table to macros are first.
- (arc_opcodes, ld [b,c] entry): Add %Q to prevent shimms.
- (arc_opcodes, st [b] entry): Likewise.
- (arc_opcodes, st [b,d] entry): Fix mask, value.
- (arc_reg_names): Add entries for r29, r30, r31, r60.
- (opcode_map, icode_map): New static globals.
- (arc_opcode_init_tables): Initialize them.
- (arc_opcode_lookup_asm, arc_opcode_lookup_dis): New functions.
- (insert_shimmoffset): Signal error if register present.
- Validate constant.
- * arc-dis.c (print_insn): Call arc_opcode_lookup_dis.
-end-sanitize-arc
-
Mon Apr 10 15:55:01 1995 Stan Shebs <shebs@andros.cygnus.com>
Merge in support for Mac MPW as a host.
* mpw-config.in: New file, MPW version of configure.in.
* mpw-make.in: New file, MPW version of Makefile.in.
-start-sanitize-arc
-Thu Apr 6 20:36:08 1995 Doug Evans <dje@chestnut.cygnus.com>
-
- * arc-dis.c (print_insn): New parameter `big_p'. Callers updated.
- Call arc_get_opcode_mach to map bfd mach number to opcode value.
- (print_insn_*): Pass bfd mach number, not opcode version.
- * arc-opc.c (arc_get_opcode_mach): New function.
-end-sanitize-arc
-
Fri Mar 31 14:23:38 1995 Ken Raeburn <raeburn@cujo.cygnus.com>
* alpha-dis.c (print_insn_alpha): Put empty statement after
(print_insn_arg): Arrays cacheFieldName and names now const.
(print_indexed): Array scales now const.
-start-sanitize-arc
-Tue Mar 7 21:14:14 1995 Doug Evans <dje@chestnut.cygnus.com>
-
- * arc-dis.c (print_insn_arc_base): Split into big and little fns.
- (print_insn_arc_{host,graphics,audio}): Likewise.
- (print_insn): Add prototype.
- (arc_get_disassembler): New arg `big_p'. Return little or big
- print fn accordingly.
- * arc-opc.c (arc_opcode_init_tables): Init arc_operand_map once.
- (arc_opcode_supported): Use ARC_OPCODE_CPU to ignore byte order.
- (arc_opval_supported): Likewise.
- * disassemble.c (disassembler): Pass big endian flag to
- arc_get_disassembler.
-end-sanitize-arc
-
Tue Mar 7 16:41:21 1995 Ian Lance Taylor <ian@cygnus.com>
* ppc-opc.c: Sort recently added instructions by minor opcode
* Makefile.in (ALL_MACHINES): Add w65-dis.o.
-start-sanitize-arc
-Fri Feb 17 12:42:25 1995 Doug Evans <dje@chestnut.cygnus.com>
-
- * arc-dis.c (arc_get_disassembler): Change argument to int,
- one of bfd_mach_arc_xxx. All callers updated.
-end-sanitize-arc
-
Thu Feb 16 17:34:41 1995 Ian Lance Taylor <ian@cygnus.com>
* mips-opc.c: Add r4650 mul instruction.
* ppc-opc.c (powerpc_opcodes): Add 403GA opcodes rfci, dccci,
mfdcr, mtdcr, icbt, iccci.
-start-sanitize-arc
-Mon Feb 13 11:09:17 1995 Doug Evans <dje@canuck.cygnus.com>
-
- * arc-dis.c (print_insn): Handle ARC_OPERAND_ADDRESS.
- * arc-opc.c (arc_operands): New operand 'J' for jump addresses.
- ('L' operand): Mark as ARC_OPERAND_ADDRESS.
- (arc_opcodes, j insn): Use 'J' operand type, not 'L'.
- (arc_opcodes, ld/st insns): Fix address writeback operand letter.
- (insert_absaddr): New function.
-
-Thu Feb 9 19:19:23 1995 Doug Evans <dje@canuck.cygnus.com>
-
- * arc-dis.c (print_insn_arc): Rename to print_insn and make static.
- New argument `cpu', pass it to arc_opcode_init_tables.
- Document byte order dependencies. Ignore unsupported insns.
- (arc_get_disassembler): New function.
- (print_insn_arc_base, print_insn_arc_host, print_insn_arc_graphics,
- print_insn_arc_audio): New functions.
- * arc-opc.c (MULTSHIFT operand): Delete.
- (UNSIGNED, SATURATION): New operands.
- (mac, mul, mul64, mulu64): New insns.
- (ext. asl, asr, lsr, ror): Only available on host and graphics cpus.
- (padc, padd, pmov, pand, psbc, psub, swap): New insns.
- (host,graphics,audio extended and auxiliary regs): Define.
- (ss, sc, mh, ml): New suffixes.
- (arc_opcode_supported, arc_opval_supported): New functions.
- (insert_multshift, extract_multshift): Deleted.
- * disassemble.c (disassembler, case bfd_arch_arc): Call
- arc_get_disassembler to get disassembler routine.
-end-sanitize-arc
-
Thu Feb 9 12:28:13 1995 Stan Shebs <shebs@andros.cygnus.com>
* i960-dis.c (struct tabent, struct sparse_tabent): Change the
* h8300-dis.c (bfd_h8_disassemble): Add support for 2 bit
immediates.
-start-sanitize-arc
-Tue Dec 20 10:36:55 1994 Doug Evans <dje@canuck.cygnus.com>
-
- * arc-dis.c (print_insn_arc): Branch offsets are relative to delay
- slot.
- * arc-opc.c (extract_reladdr): New function.
- (insert_reladdr): Store address right-shifted by 2.
-end-sanitize-arc
-
Tue Dec 20 11:25:12 1994 Ian Lance Taylor <ian@sanguine.cygnus.com>
* mips-opc.c: Add dli as a synonym for li.
-start-sanitize-arc
-Mon Dec 19 12:35:51 1994 Doug Evans <dje@canuck.cygnus.com>
-
- * arc-opc.c (insertion fns): Pass pointer to value's table entry.
- All uses changed.
- (extraction fns): Insn argument now array of two words. Return pointer
- to value's table entry. All uses changed.
- (arc_opcode_lookup_suffix): Exported for arc-dis.c.
- (insert_multshift, extract_multshift): New fns.
- (arc_operands): Add support for cache bypass suffix. Add support for
- predefined aux regs. Modifier bits moved to flags field.
- (arc_opcodes): Likewise.
- Add mul/mulu/shift insns. Syntax of zero/sign extension insns changed.
- New insn rlc. Update to syntax in programmer's manual.
- (arc_reg_names): Fix typo in lp_count. Add predefined aux regs.
- (arc_suffixes): New synonyms lo,hs for cs,cc. New suffix for cache
- bypass.
- (arc_opcode_init_tables): New argument to indicate cpu type.
- (insert_reg): Handle predefined aux regs.
- (extract_reg): Likewise.
- (lookup_register): New fn.
- * arc-dis.c (arc_condition_codes): Deleted.
- (print_insn_arc): Handle insns with 32 bit immediate constants better.
- Clean up modifier handling. Handle predefined aux regs.
-end-sanitize-arc
-
Thu Dec 8 18:23:31 1994 Ken Raeburn <raeburn@cujo.cygnus.com>
* alpha-dis.c (print_insn_alpha): Handle call_pal instruction, and
* m68k-dis.c (print_insn_arg, case 'J'): Handle buscr and pcr
control registers.
-start-sanitize-arc
-Tue Nov 29 18:02:43 1994 Doug Evans <dje@canuck.cygnus.com>
-
- * configure.in: Add ARC support.
- * disassemble.c: Likewise.
- * arc-dis.c, arc-opc.c: New files.
-end-sanitize-arc
-
Wed Nov 23 22:34:51 1994 Steve Chamberlain (sac@jonny.cygnus.com)
* sh-opc.h (mov.l gbr): Get direction right.
projects / external / binutils.git / blobdiff