+2018-07-30 Jim Wilson <jimw@sifive.com>
+
+ * riscv-dis.c (riscv_disassemble_insn): Set insn_type and data_size
+ fields.
+ * riscv-opc.c (riscv_opcodes): Use new INSN_* flags to annotate insns.
+
+2018-07-30 Andrew Jenner <andrew@codesourcery.com>
+
+ * Makefile.am (TARGET_LIBOPCODES_CFILES): Add csky-dis.c.
+ * Makefile.in: Regenerated.
+ * configure.ac: Add C-SKY.
+ * configure: Regenerated.
+ * csky-dis.c: New file.
+ * csky-opc.h: New file.
+ * disassemble.c (ARCH_csky): Define.
+ (disassembler, disassemble_init_for_target): Add case for ARCH_csky.
+ * disassemble.h (print_insn_csky, csky_get_disassembler): Declare.
+
+2018-07-27 Alan Modra <amodra@gmail.com>
+
+ * ppc-opc.c (insert_sprbat): Correct function parameter and
+ return type.
+ (extract_sprbat): Likewise, variable too.
+
+2018-07-26 Alex Chadwick <Alex.Chadwick@cl.cam.ac.uk>
+ Alan Modra <amodra@gmail.com>
+
+ * ppc-dis.c (ppc_opts): Add -mgekko and -mbroadway.
+ (powerpc_init_dialect): Handle bfd_mach_ppc_750.
+ * ppc-opc.c (insert_sprbat, extract_sprbat): New functions to
+ support disjointed BAT.
+ (powerpc_operands): Allow extra bit in SPRBAT_MASK. Add SPRGQR.
+ (XSPRGQR_MASK, GEKKO, BROADWAY): Define.
+ (powerpc_opcodes): Add 750cl extended mnemonics for spr access.
+
+2018-07-25 H.J. Lu <hongjiu.lu@intel.com>
+ Igor Tsimbalist <igor.v.tsimbalist@intel.com>
+
+ * i386-gen.c (adjust_broadcast_modifier): New function.
+ (process_i386_opcode_modifier): Add an argument for operands.
+ Adjust the Broadcast value based on operands.
+ (output_i386_opcode): Pass operand_types to
+ process_i386_opcode_modifier.
+ (process_i386_opcodes): Pass NULL as operands to
+ process_i386_opcode_modifier.
+ * i386-opc.h (BYTE_BROADCAST): New.
+ (WORD_BROADCAST): Likewise.
+ (DWORD_BROADCAST): Likewise.
+ (QWORD_BROADCAST): Likewise.
+ (i386_opcode_modifier): Expand broadcast to 3 bits.
+ * i386-tbl.h: Regenerated.
+
+2018-07-24 Alan Modra <amodra@gmail.com>
+
+ PR 23430
+ * or1k-desc.h: Regenerate.
+
+2018-07-24 Jan Beulich <jbeulich@suse.com>
+
+ * i386-dis-evex.h (evex_table): Add %LQ to vcvtsi2ss, vcvtsi2sd,
+ vcvtusi2ss, and vcvtusi2sd.
+ * i386-opc.tbl (vcvtsi2sd, vcvtusi2sd, vcvtsi2ss, vcvtusi2ss):
+ Convert AVX512F variants to distinct CpuNo64 and Cpu64 forms.
+ * i386-tbl.h: Re-generate.
+
+2018-07-23 Claudiu Zissulescu <claziss@synopsys.com>
+
+ * arc-opc.c (extract_w6): Fix extending the sign.
+
+2018-07-23 Claudiu Zissulescu <claziss@synopsys.com>
+
+ * arc-tbl.h (vewt): Allow it for ARC EM family.
+
+2018-07-23 Alan Modra <amodra@gmail.com>
+
+ PR 23419
+ * ppc-opc.c (powerpc_opcodes): Add mtupmc/mfupmc/mfpmc extended
+ opcode variants for mtspr/mfspr encodings.
+
+2018-07-20 Chenghua Xu <paul.hua.gm@gmail.com>
+ Maciej W. Rozycki <macro@mips.com>
+
+ * mips-dis.c (mips_arch_choices): Add MMI to loongson2f and
+ loongson3a descriptors.
+ (parse_mips_ase_option): Handle -M loongson-mmi option.
+ (print_mips_disassembler_options): Document -M loongson-mmi.
+ * mips-opc.c (LMMI): New macro.
+ (mips_opcodes): Replace IL2F|IL3A marking with LMMI for MMI
+ instructions.
+
+2018-07-19 Jan Beulich <jbeulich@suse.com>
+
+ * i386-opc.tbl (vcvtpd2dq, vcvtpd2ps, vcvttpd2dq, vcvtpd2udq,
+ vcvtqq2ps, vcvtuqq2ps): Fold 128- and 256-bit templates. Drop
+ IgnoreSize and [XYZ]MMword where applicable.
+ * i386-tbl.h: Re-generate.
+
+2018-07-19 Jan Beulich <jbeulich@suse.com>
+
+ * i386-opc.tbl (vfpclasspd, vfpclassps): Fold.
+ (vfpclasspdz, vfpclasspsz): Drop IgnoreSize and ZmmWord.
+ (vfpclasspdx, vfpclasspsx): Drop IgnoreSize and XmmWord.
+ (vfpclasspdy, vfpclasspsy): Drop IgnoreSize and YmmWord.
+ * i386-tbl.h: Re-generate.
+
+2018-07-19 Jan Beulich <jbeulich@suse.com>
+
+ * i386-opc.tbl: Fold AVX512IFMA, AVX512VBMI, AVX512_VPOPCNTDQ,
+ AVX512_VBMI2, AVX512_VNNI, AVX512_BITALG, GFNI, VAES, and
+ VPCLMULQDQ templates into their respective AVX512VL counterparts
+ where possible, using Disp8ShiftVL and CheckRegSize instead of
+ Evex= plus Disp8MemShift= (plus often IgnoreSize) as appropriate.
+ * i386-tbl.h: Re-generate.
+
+2018-07-19 Jan Beulich <jbeulich@suse.com>
+
+ * i386-opc.tbl: Fold AVX512DQ templates into their respective
+ AVX512VL counterparts where possible, using Disp8ShiftVL and
+ CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
+ IgnoreSize) as appropriate.
+ * i386-tbl.h: Re-generate.
+
+2018-07-19 Jan Beulich <jbeulich@suse.com>
+
+ * i386-opc.tbl: Fold AVX512BW templates into their respective
+ AVX512VL counterparts where possible, using Disp8ShiftVL and
+ CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
+ IgnoreSize) as appropriate.
+ * i386-tbl.h: Re-generate.
+
+2018-07-19 Jan Beulich <jbeulich@suse.com>
+
+ * i386-opc.tbl: Fold AVX512CD templates into their respective
+ AVX512VL counterparts where possible, using Disp8ShiftVL and
+ CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
+ IgnoreSize) as appropriate.
+ * i386-tbl.h: Re-generate.
+
+2018-07-19 Jan Beulich <jbeulich@suse.com>
+
+ * i386-opc.h (DISP8_SHIFT_VL): New.
+ * i386-opc.tbl (Disp8ShiftVL): Define.
+ (various): Fold AVX512VL templates into their respective
+ AVX512F counterparts where possible, using Disp8ShiftVL and
+ CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
+ IgnoreSize) as appropriate.
+ * i386-tbl.h: Re-generate.
+
+2018-07-19 Jan Beulich <jbeulich@suse.com>
+
+ * Makefile.am: Change dependencies and rule for
+ $(srcdir)/i386-init.h.
+ * Makefile.in: Re-generate.
+ * i386-gen.c (process_i386_opcodes): New local variable
+ "marker". Drop opening of input file. Recognize marker and line
+ number directives.
+ * i386-opc.tbl (OPCODE_I386_H): Define.
+ (i386-opc.h): Include it.
+ (None): Undefine.
+
2018-07-18 H.J. Lu <hongjiu.lu@intel.com>
PR gas/23418
projects / external / binutils.git / blobdiff