#include <common.h>
#include <nand.h>
-#include <asm-arm/arch/mx31-regs.h>
+#include <asm/arch/imx-regs.h>
#include <asm/io.h>
#include <fsl_nfc.h>
-static struct fsl_nfc_regs *nfc;
+static struct fsl_nfc_regs *const nfc = (void *)NFC_BASE_ADDR;
static void nfc_wait_ready(void)
{
uint32_t tmp;
- while (!(readw(&nfc->nand_flash_config2) & NFC_INT))
+ while (!(readnfc(&nfc->config2) & NFC_V1_V2_CONFIG2_INT))
;
/* Reset interrupt flag */
- tmp = readw(&nfc->nand_flash_config2);
- tmp &= ~NFC_INT;
- writew(tmp, &nfc->nand_flash_config2);
+ tmp = readnfc(&nfc->config2);
+ tmp &= ~NFC_V1_V2_CONFIG2_INT;
+ writenfc(tmp, &nfc->config2);
}
static void nfc_nand_init(void)
{
+#if defined(MXC_NFC_V2_1)
+ int ecc_per_page = CONFIG_SYS_NAND_PAGE_SIZE / 512;
+ int config1;
+
+ writenfc(CONFIG_SYS_NAND_SPARE_SIZE / 2, &nfc->spare_area_size);
+
+ /* unlocking RAM Buff */
+ writenfc(0x2, &nfc->config);
+
+ /* hardware ECC checking and correct */
+ config1 = readnfc(&nfc->config1) | NFC_V1_V2_CONFIG1_ECC_EN |
+ NFC_V1_V2_CONFIG1_INT_MSK | NFC_V2_CONFIG1_ONE_CYCLE |
+ NFC_V2_CONFIG1_FP_INT;
+ /*
+ * if spare size is larger that 16 bytes per 512 byte hunk
+ * then use 8 symbol correction instead of 4
+ */
+ if (CONFIG_SYS_NAND_SPARE_SIZE / ecc_per_page > 16)
+ config1 &= ~NFC_V2_CONFIG1_ECC_MODE_4;
+ else
+ config1 |= NFC_V2_CONFIG1_ECC_MODE_4;
+ writenfc(config1, &nfc->config1);
+#elif defined(MXC_NFC_V1)
/* unlocking RAM Buff */
- writew(0x2, &nfc->configuration);
+ writenfc(0x2, &nfc->config);
/* hardware ECC checking and correct */
- writew(NFC_ECC_EN, &nfc->nand_flash_config1);
+ writenfc(NFC_V1_V2_CONFIG1_ECC_EN | NFC_V1_V2_CONFIG1_INT_MSK,
+ &nfc->config1);
+#endif
}
static void nfc_nand_command(unsigned short command)
{
- writew(command, &nfc->flash_cmd);
- writew(NFC_CMD, &nfc->nand_flash_config2);
+ writenfc(command, &nfc->flash_cmd);
+ writenfc(NFC_CMD, &nfc->operation);
+ nfc_wait_ready();
+}
+
+static void nfc_nand_address(unsigned short address)
+{
+ writenfc(address, &nfc->flash_addr);
+ writenfc(NFC_ADDR, &nfc->operation);
nfc_wait_ready();
}
{
unsigned int page_count;
- writew(0x00, &nfc->flash_cmd);
- writew(NFC_ADDR, &nfc->nand_flash_config2);
- nfc_wait_ready();
+ nfc_nand_address(0x00);
- /* code only for 2kb flash */
- if (CONFIG_SYS_NAND_PAGE_SIZE == 0x800) {
- writew(0x00, &nfc->flash_add);
- writew(NFC_ADDR, &nfc->nand_flash_config2);
- nfc_wait_ready();
- }
+ /* code only for large page flash */
+ if (CONFIG_SYS_NAND_PAGE_SIZE > 512)
+ nfc_nand_address(0x00);
page_count = CONFIG_SYS_NAND_SIZE / CONFIG_SYS_NAND_PAGE_SIZE;
if (page_address <= page_count) {
page_count--; /* transform 0x01000000 to 0x00ffffff */
do {
- writew(page_address & 0xff, &nfc->flash_add);
- writew(NFC_ADDR, &nfc->nand_flash_config2);
- nfc_wait_ready();
+ nfc_nand_address(page_address & 0xff);
page_address = page_address >> 8;
page_count = page_count >> 8;
} while (page_count);
}
+
+ nfc_nand_address(0x00);
}
static void nfc_nand_data_output(void)
{
+#ifdef NAND_MXC_2K_MULTI_CYCLE
int i;
+#endif
+ writenfc(0, &nfc->buf_addr);
+ writenfc(NFC_OUTPUT, &nfc->operation);
+ nfc_wait_ready();
+#ifdef NAND_MXC_2K_MULTI_CYCLE
/*
- * The NAND controller requires four output commands for
- * large page devices.
+ * This NAND controller requires multiple input commands
+ * for pages larger than 512 bytes.
*/
- for (i = 0; i < (CONFIG_SYS_NAND_PAGE_SIZE / 512); i++) {
- writew(NFC_ECC_EN, &nfc->nand_flash_config1);
- writew(i, &nfc->buffer_address); /* read in i:th buffer */
- writew(NFC_OUTPUT, &nfc->nand_flash_config2);
+ for (i = 1; i < CONFIG_SYS_NAND_PAGE_SIZE / 512; i++) {
+ writenfc(i, &nfc->buf_addr);
+ writenfc(NFC_OUTPUT, &nfc->operation);
nfc_wait_ready();
}
+#endif
}
static int nfc_nand_check_ecc(void)
{
- return readw(&nfc->ecc_status_result);
+#if defined(MXC_NFC_V1)
+ u16 ecc_status = readw(&nfc->ecc_status_result);
+ return (ecc_status & 0x3) == 2 || (ecc_status >> 2) == 2;
+#elif defined(MXC_NFC_V2_1)
+ u32 ecc_status = readl(&nfc->ecc_status_result);
+ int ecc_per_page = CONFIG_SYS_NAND_PAGE_SIZE / 512;
+ int err_limit = CONFIG_SYS_NAND_SPARE_SIZE / ecc_per_page > 16 ? 8 : 4;
+ int subpages = CONFIG_SYS_NAND_PAGE_SIZE / 512;
+
+ do {
+ if ((ecc_status & 0xf) > err_limit)
+ return 1;
+ ecc_status >>= 4;
+ } while (--subpages);
+
+ return 0;
+#endif
}
-static int nfc_read_page(unsigned int page_address, unsigned char *buf)
+static void nfc_nand_read_page(unsigned int page_address)
{
- int i;
- u32 *src;
- u32 *dst;
-
- writew(0, &nfc->buffer_address); /* read in first 0 buffer */
+ /* read in first 0 buffer */
+ writenfc(0, &nfc->buf_addr);
nfc_nand_command(NAND_CMD_READ0);
nfc_nand_page_address(page_address);
- if (CONFIG_SYS_NAND_PAGE_SIZE == 0x800)
+ if (CONFIG_SYS_NAND_PAGE_SIZE > 512)
nfc_nand_command(NAND_CMD_READSTART);
nfc_nand_data_output(); /* fill the main buffer 0 */
+}
+
+static int nfc_read_page(unsigned int page_address, unsigned char *buf)
+{
+ int i;
+ u32 *src;
+ u32 *dst;
+
+ nfc_nand_read_page(page_address);
if (nfc_nand_check_ecc())
return -1;
- src = &nfc->main_area0[0];
+ src = (u32 *)&nfc->main_area[0][0];
dst = (u32 *)buf;
/* main copy loop from NAND-buffer to SDRAM memory */
- for (i = 0; i < (CONFIG_SYS_NAND_PAGE_SIZE / 4); i++) {
+ for (i = 0; i < CONFIG_SYS_NAND_PAGE_SIZE / 4; i++) {
writel(readl(src), dst);
src++;
dst++;
/* Check the first two pages for bad block markers */
for (page = pagenumber; page < pagenumber + 2; page++) {
- writew(0, &nfc->buffer_address); /* read in first 0 buffer */
- nfc_nand_command(NAND_CMD_READ0);
- nfc_nand_page_address(page);
-
- if (CONFIG_SYS_NAND_PAGE_SIZE == 0x800)
- nfc_nand_command(NAND_CMD_READSTART);
+ nfc_nand_read_page(page);
- nfc_nand_data_output(); /* fill the main buffer 0 */
-
- src = &nfc->spare_area0[0];
+ src = (u32 *)&nfc->spare_area[0][0];
/*
* IMPORTANT NOTE: The nand flash controller uses a non-
unsigned int maxpages = CONFIG_SYS_NAND_SIZE /
CONFIG_SYS_NAND_PAGE_SIZE;
- nfc = (void *)NFC_BASE_ADDR;
-
nfc_nand_init();
/* Convert to page number */
page = from / CONFIG_SYS_NAND_PAGE_SIZE;
i = 0;
- while (i < (size / CONFIG_SYS_NAND_PAGE_SIZE)) {
+ while (i < size / CONFIG_SYS_NAND_PAGE_SIZE) {
if (nfc_read_page(page, buf) < 0)
return -1;
if (!(page % CONFIG_SYS_NAND_PAGE_COUNT)) {
/*
* Yes, new block. See if this block is good. If not,
- * loop until we find i good block.
+ * loop until we find a good block.
*/
while (is_badblock(page)) {
page = page + CONFIG_SYS_NAND_PAGE_COUNT;
return 0;
}
+#if defined(CONFIG_ARM)
+void board_init_f (ulong bootflag)
+{
+ relocate_code (CONFIG_SYS_TEXT_BASE - TOTAL_MALLOC_LEN, NULL,
+ CONFIG_SYS_TEXT_BASE);
+}
+#endif
+
/*
* The main entry for NAND booting. It's necessary that SDRAM is already
* configured and available since this code loads the main U-Boot image
{
__attribute__((noreturn)) void (*uboot)(void);
- nfc = (void *)NFC_BASE_ADDR;
-
/*
* CONFIG_SYS_NAND_U_BOOT_OFFS and CONFIG_SYS_NAND_U_BOOT_SIZE must
* be aligned to full pages
projects / kernel / u-boot.git / blobdiff