-\r
-/****************************************************************************\r
- * Copyright (C) 2003-2006 by XGI Technology, Taiwan. \r
- * *\r
- * All Rights Reserved. *\r
- * *\r
- * Permission is hereby granted, free of charge, to any person obtaining\r
- * a copy of this software and associated documentation files (the \r
- * "Software"), to deal in the Software without restriction, including \r
- * without limitation on the rights to use, copy, modify, merge, \r
- * publish, distribute, sublicense, and/or sell copies of the Software, \r
- * and to permit persons to whom the Software is furnished to do so, \r
- * subject to the following conditions: \r
- * *\r
- * The above copyright notice and this permission notice (including the \r
- * next paragraph) shall be included in all copies or substantial \r
- * portions of the Software. \r
- * *\r
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, \r
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF \r
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND \r
- * NON-INFRINGEMENT. IN NO EVENT SHALL XGI AND/OR \r
- * ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, \r
- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, \r
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER \r
- * DEALINGS IN THE SOFTWARE. \r
- ***************************************************************************/\r
-\r
-#ifndef _XGI_DRV_H_\r
-#define _XGI_DRV_H_\r
-\r
-#define XGI_MAJOR_VERSION 0\r
-#define XGI_MINOR_VERSION 7\r
-#define XGI_PATCHLEVEL 5\r
-\r
-#define XGI_DRV_VERSION "0.7.5"\r
-\r
-#ifndef XGI_DRV_NAME\r
-#define XGI_DRV_NAME "xgi"\r
-#endif\r
-\r
-/*\r
- * xgi reserved major device number, Set this to 0 to\r
- * request dynamic major number allocation.\r
- */\r
-#ifndef XGI_DEV_MAJOR\r
-#define XGI_DEV_MAJOR 0\r
-#endif\r
-\r
-#ifndef XGI_MAX_DEVICES\r
-#define XGI_MAX_DEVICES 1\r
-#endif\r
-\r
-/* Jong 06/06/2006 */\r
-/* #define XGI_DEBUG */\r
-\r
-#ifndef PCI_VENDOR_ID_XGI\r
-/*\r
-#define PCI_VENDOR_ID_XGI 0x1023\r
-*/\r
-#define PCI_VENDOR_ID_XGI 0x18CA\r
-\r
-#endif\r
-\r
-#ifndef PCI_DEVICE_ID_XP5\r
-#define PCI_DEVICE_ID_XP5 0x2200\r
-#endif\r
-\r
-#ifndef PCI_DEVICE_ID_XG47\r
-#define PCI_DEVICE_ID_XG47 0x0047\r
-#endif\r
-\r
-/* Macros to make printk easier */\r
-#define XGI_ERROR(fmt, arg...) \\r
- printk(KERN_ERR "[" XGI_DRV_NAME ":%s] *ERROR* " fmt, __FUNCTION__, ##arg)\r
-\r
-#define XGI_MEM_ERROR(area, fmt, arg...) \\r
- printk(KERN_ERR "[" XGI_DRV_NAME ":%s] *ERROR* " fmt, __FUNCTION__, ##arg)\r
-\r
-/* #define XGI_DEBUG */ \r
-\r
-#ifdef XGI_DEBUG\r
-#define XGI_INFO(fmt, arg...) \\r
- printk(KERN_ALERT "[" XGI_DRV_NAME ":%s] " fmt, __FUNCTION__, ##arg)\r
-/* printk(KERN_INFO "[" XGI_DRV_NAME ":%s] " fmt, __FUNCTION__, ##arg) */\r
-#else\r
-#define XGI_INFO(fmt, arg...) do { } while (0)\r
-#endif\r
-\r
-/* device name length; must be atleast 8 */\r
-#define XGI_DEVICE_NAME_LENGTH 40\r
-\r
-/* need a fake device number for control device; just to flag it for msgs */\r
-#define XGI_CONTROL_DEVICE_NUMBER 100\r
-\r
-typedef struct {\r
- U32 base; // pcie base is different from fb base\r
- U32 size;\r
- U8 *vbase;\r
-} xgi_aperture_t;\r
-\r
-typedef struct xgi_screen_info_s {\r
- U32 scrn_start;\r
- U32 scrn_xres;\r
- U32 scrn_yres;\r
- U32 scrn_bpp;\r
- U32 scrn_pitch;\r
-} xgi_screen_info_t;\r
-\r
-typedef struct xgi_sarea_info_s {\r
- U32 bus_addr;\r
- U32 size;\r
-} xgi_sarea_info_t;\r
-\r
-typedef struct xgi_info_s {\r
- struct pci_dev *dev;\r
- int flags;\r
- int device_number;\r
- int bus; /* PCI config info */\r
- int slot;\r
- int vendor_id;\r
- U32 device_id;\r
- U8 revision_id;\r
-\r
- /* physical characteristics */\r
- xgi_aperture_t mmio;\r
- xgi_aperture_t fb;\r
- xgi_aperture_t pcie;\r
- xgi_screen_info_t scrn_info;\r
- xgi_sarea_info_t sarea_info;\r
-\r
- /* look up table parameters */\r
- U32 *lut_base;\r
- U32 lutPageSize;\r
- U32 lutPageOrder;\r
- U32 isLUTInLFB;\r
- U32 sdfbPageSize;\r
-\r
- U32 pcie_config;\r
- U32 pcie_status;\r
- U32 irq;\r
-\r
- atomic_t use_count;\r
-\r
- /* keep track of any pending bottom halfes */\r
- struct tasklet_struct tasklet;\r
-\r
- spinlock_t info_lock;\r
-\r
- struct semaphore info_sem;\r
- struct semaphore fb_sem;\r
- struct semaphore pcie_sem;\r
-} xgi_info_t;\r
-\r
-typedef struct xgi_ioctl_post_vbios {\r
- U32 bus;\r
- U32 slot;\r
-} xgi_ioctl_post_vbios_t;\r
-\r
-typedef enum xgi_mem_location_s\r
-{\r
- NON_LOCAL = 0,\r
- LOCAL = 1,\r
- INVALID = 0x7fffffff\r
-} xgi_mem_location_t;\r
-\r
-enum PcieOwner\r
-{\r
- PCIE_2D = 0,\r
- /*\r
- PCIE_3D should not begin with 1,\r
- 2D alloc pcie memory will use owner 1.\r
- */\r
- PCIE_3D = 11,/*vetex buf*/\r
- PCIE_3D_CMDLIST = 12,\r
- PCIE_3D_SCRATCHPAD = 13,\r
- PCIE_3D_TEXTURE = 14,\r
- PCIE_INVALID = 0x7fffffff\r
-};\r
-\r
-typedef struct xgi_mem_req_s {\r
- xgi_mem_location_t location;\r
- unsigned long size;\r
- unsigned long is_front;\r
- enum PcieOwner owner;\r
- unsigned long pid;\r
-} xgi_mem_req_t;\r
-\r
-typedef struct xgi_mem_alloc_s {\r
- xgi_mem_location_t location;\r
- unsigned long size;\r
- unsigned long bus_addr;\r
- unsigned long hw_addr;\r
- unsigned long pid;\r
-} xgi_mem_alloc_t;\r
-\r
-typedef struct xgi_chip_info_s {\r
- U32 device_id;\r
- char device_name[32];\r
- U32 vendor_id;\r
- U32 curr_display_mode; //Singe, DualView(Contained), MHS\r
- U32 fb_size;\r
- U32 sarea_bus_addr;\r
- U32 sarea_size;\r
-} xgi_chip_info_t;\r
-\r
-typedef struct xgi_opengl_cmd_s {\r
- U32 cmd;\r
-} xgi_opengl_cmd_t;\r
-\r
-typedef struct xgi_mmio_info_s {\r
- xgi_opengl_cmd_t cmd_head;\r
- void *mmioBase;\r
- int size;\r
-} xgi_mmio_info_t;\r
-\r
-typedef enum {\r
- BTYPE_2D = 0,\r
- BTYPE_3D = 1,\r
- BTYPE_FLIP = 2,\r
- BTYPE_CTRL = 3,\r
- BTYPE_NONE = 0x7fffffff\r
-}BATCH_TYPE;\r
-\r
-typedef struct xgi_cmd_info_s {\r
- BATCH_TYPE _firstBeginType;\r
- U32 _firstBeginAddr;\r
- U32 _firstSize;\r
- U32 _curDebugID;\r
- U32 _lastBeginAddr;\r
- U32 _beginCount;\r
-} xgi_cmd_info_t;\r
-\r
-typedef struct xgi_state_info_s {\r
- U32 _fromState;\r
- U32 _toState;\r
-} xgi_state_info_t;\r
-\r
-typedef struct cpu_info_s {\r
- U32 _eax;\r
- U32 _ebx;\r
- U32 _ecx;\r
- U32 _edx;\r
-} cpu_info_t;\r
-\r
-typedef struct xgi_mem_pid_s {\r
- struct list_head list;\r
- xgi_mem_location_t location;\r
- unsigned long bus_addr;\r
- unsigned long pid;\r
-} xgi_mem_pid_t;\r
-\r
-/*\r
- * Ioctl definitions\r
- */\r
-\r
-#define XGI_IOCTL_MAGIC 'x' /* use 'x' as magic number */\r
-\r
-#define XGI_IOCTL_BASE 0\r
-#define XGI_ESC_DEVICE_INFO (XGI_IOCTL_BASE + 0)\r
-#define XGI_ESC_POST_VBIOS (XGI_IOCTL_BASE + 1)\r
-\r
-#define XGI_ESC_FB_INIT (XGI_IOCTL_BASE + 2)\r
-#define XGI_ESC_FB_ALLOC (XGI_IOCTL_BASE + 3)\r
-#define XGI_ESC_FB_FREE (XGI_IOCTL_BASE + 4)\r
-#define XGI_ESC_PCIE_INIT (XGI_IOCTL_BASE + 5)\r
-#define XGI_ESC_PCIE_ALLOC (XGI_IOCTL_BASE + 6)\r
-#define XGI_ESC_PCIE_FREE (XGI_IOCTL_BASE + 7)\r
-#define XGI_ESC_SUBMIT_CMDLIST (XGI_IOCTL_BASE + 8)\r
-#define XGI_ESC_PUT_SCREEN_INFO (XGI_IOCTL_BASE + 9)\r
-#define XGI_ESC_GET_SCREEN_INFO (XGI_IOCTL_BASE + 10)\r
-#define XGI_ESC_GE_RESET (XGI_IOCTL_BASE + 11)\r
-#define XGI_ESC_SAREA_INFO (XGI_IOCTL_BASE + 12)\r
-#define XGI_ESC_DUMP_REGISTER (XGI_IOCTL_BASE + 13)\r
-#define XGI_ESC_DEBUG_INFO (XGI_IOCTL_BASE + 14)\r
-#define XGI_ESC_TEST_RWINKERNEL (XGI_IOCTL_BASE + 16)\r
-#define XGI_ESC_STATE_CHANGE (XGI_IOCTL_BASE + 17)\r
-#define XGI_ESC_MMIO_INFO (XGI_IOCTL_BASE + 18)\r
-#define XGI_ESC_PCIE_CHECK (XGI_IOCTL_BASE + 19)\r
-#define XGI_ESC_CPUID (XGI_IOCTL_BASE + 20)\r
-#define XGI_ESC_MEM_COLLECT (XGI_IOCTL_BASE + 21)\r
-\r
-#define XGI_IOCTL_DEVICE_INFO _IOR(XGI_IOCTL_MAGIC, XGI_ESC_DEVICE_INFO, xgi_chip_info_t)\r
-#define XGI_IOCTL_POST_VBIOS _IO(XGI_IOCTL_MAGIC, XGI_ESC_POST_VBIOS)\r
-\r
-#define XGI_IOCTL_FB_INIT _IO(XGI_IOCTL_MAGIC, XGI_ESC_FB_INIT)\r
-#define XGI_IOCTL_FB_ALLOC _IOWR(XGI_IOCTL_MAGIC, XGI_ESC_FB_ALLOC, xgi_mem_req_t)\r
-#define XGI_IOCTL_FB_FREE _IOW(XGI_IOCTL_MAGIC, XGI_ESC_FB_FREE, unsigned long)\r
-\r
-#define XGI_IOCTL_PCIE_INIT _IO(XGI_IOCTL_MAGIC, XGI_ESC_PCIE_INIT)\r
-#define XGI_IOCTL_PCIE_ALLOC _IOWR(XGI_IOCTL_MAGIC, XGI_ESC_PCIE_ALLOC, xgi_mem_req_t)\r
-#define XGI_IOCTL_PCIE_FREE _IOW(XGI_IOCTL_MAGIC, XGI_ESC_PCIE_FREE, unsigned long)\r
-\r
-#define XGI_IOCTL_PUT_SCREEN_INFO _IOW(XGI_IOCTL_MAGIC, XGI_ESC_PUT_SCREEN_INFO, xgi_screen_info_t)\r
-#define XGI_IOCTL_GET_SCREEN_INFO _IOR(XGI_IOCTL_MAGIC, XGI_ESC_GET_SCREEN_INFO, xgi_screen_info_t)\r
-\r
-#define XGI_IOCTL_GE_RESET _IO(XGI_IOCTL_MAGIC, XGI_ESC_GE_RESET)\r
-#define XGI_IOCTL_SAREA_INFO _IOW(XGI_IOCTL_MAGIC, XGI_ESC_SAREA_INFO, xgi_sarea_info_t)\r
-#define XGI_IOCTL_DUMP_REGISTER _IO(XGI_IOCTL_MAGIC, XGI_ESC_DUMP_REGISTER)\r
-#define XGI_IOCTL_DEBUG_INFO _IO(XGI_IOCTL_MAGIC, XGI_ESC_DEBUG_INFO)\r
-#define XGI_IOCTL_MMIO_INFO _IOR(XGI_IOCTL_MAGIC, XGI_ESC_MMIO_INFO, xgi_mmio_info_t)\r
-\r
-#define XGI_IOCTL_SUBMIT_CMDLIST _IOWR(XGI_IOCTL_MAGIC, XGI_ESC_SUBMIT_CMDLIST, xgi_cmd_info_t)\r
-#define XGI_IOCTL_TEST_RWINKERNEL _IOWR(XGI_IOCTL_MAGIC, XGI_ESC_TEST_RWINKERNEL, unsigned long)\r
-#define XGI_IOCTL_STATE_CHANGE _IOWR(XGI_IOCTL_MAGIC, XGI_ESC_STATE_CHANGE, xgi_state_info_t)\r
-\r
-#define XGI_IOCTL_PCIE_CHECK _IO(XGI_IOCTL_MAGIC, XGI_ESC_PCIE_CHECK)\r
-#define XGI_IOCTL_CPUID _IOWR(XGI_IOCTL_MAGIC, XGI_ESC_CPUID, cpu_info_t)\r
-#define XGI_IOCTL_MAXNR 30\r
-\r
-/*\r
- * flags\r
- */\r
-#define XGI_FLAG_OPEN 0x0001\r
-#define XGI_FLAG_NEEDS_POSTING 0x0002\r
-#define XGI_FLAG_WAS_POSTED 0x0004\r
-#define XGI_FLAG_CONTROL 0x0010\r
-#define XGI_FLAG_MAP_REGS_EARLY 0x0200\r
-\r
-/* mmap(2) offsets */\r
-\r
-#define IS_IO_OFFSET(info, offset, length) \\r
- (((offset) >= (info)->mmio.base) \\r
- && (((offset) + (length)) <= (info)->mmio.base + (info)->mmio.size))\r
-\r
-/* Jong 06/14/2006 */\r
-/* (info)->fb.base is a base address for physical (bus) address space */\r
-/* what's the definition of offest? on physical (bus) address space or HW address space */\r
-/* Jong 06/15/2006; use HW address space */\r
-#define IS_FB_OFFSET(info, offset, length) \\r
- (((offset) >= 0) \\r
- && (((offset) + (length)) <= (info)->fb.size))\r
-#if 0\r
-#define IS_FB_OFFSET(info, offset, length) \\r
- (((offset) >= (info)->fb.base) \\r
- && (((offset) + (length)) <= (info)->fb.base + (info)->fb.size))\r
-#endif\r
-\r
-#define IS_PCIE_OFFSET(info, offset, length) \\r
- (((offset) >= (info)->pcie.base) \\r
- && (((offset) + (length)) <= (info)->pcie.base + (info)->pcie.size))\r
-\r
-extern int xgi_fb_heap_init(xgi_info_t *info);\r
-extern void xgi_fb_heap_cleanup(xgi_info_t *info);\r
-\r
-extern void xgi_fb_alloc(xgi_info_t *info, xgi_mem_req_t *req, xgi_mem_alloc_t *alloc);\r
-extern void xgi_fb_free(xgi_info_t *info, unsigned long offset);\r
-extern void xgi_mem_collect(xgi_info_t *info, unsigned int *pcnt);\r
-\r
-extern int xgi_pcie_heap_init(xgi_info_t *info);\r
-extern void xgi_pcie_heap_cleanup(xgi_info_t *info);\r
-\r
-extern void xgi_pcie_alloc(xgi_info_t *info, unsigned long size, enum PcieOwner owner, xgi_mem_alloc_t *alloc);\r
-extern void xgi_pcie_free(xgi_info_t *info, unsigned long offset);\r
-extern void xgi_pcie_heap_check(void);\r
-extern void *xgi_find_pcie_block(xgi_info_t *info, unsigned long address);\r
-extern void *xgi_find_pcie_virt(xgi_info_t *info, unsigned long address);\r
-\r
-extern void xgi_read_pcie_mem(xgi_info_t *info, xgi_mem_req_t *req);\r
-extern void xgi_write_pcie_mem(xgi_info_t *info, xgi_mem_req_t *req);\r
-\r
-extern void xgi_test_rwinkernel(xgi_info_t *info, unsigned long address);\r
-\r
-#endif\r
+/****************************************************************************
+ * Copyright (C) 2003-2006 by XGI Technology, Taiwan.
+ *
+ * All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining
+ * a copy of this software and associated documentation files (the
+ * "Software"), to deal in the Software without restriction, including
+ * without limitation on the rights to use, copy, modify, merge,
+ * publish, distribute, sublicense, and/or sell copies of the Software,
+ * and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the
+ * next paragraph) shall be included in all copies or substantial
+ * portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
+ * XGI AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ ***************************************************************************/
+
+#ifndef _XGI_DRV_H_
+#define _XGI_DRV_H_
+
+#include "drmP.h"
+#include "drm.h"
+#include "drm_sman.h"
+
+#define DRIVER_AUTHOR "Andrea Zhang <andrea_zhang@macrosynergy.com>"
+
+#define DRIVER_NAME "xgi"
+#define DRIVER_DESC "XGI XP5 / XP10 / XG47"
+#define DRIVER_DATE "20080612"
+
+#define DRIVER_MAJOR 1
+#define DRIVER_MINOR 2
+#define DRIVER_PATCHLEVEL 0
+
+#include "xgi_cmdlist.h"
+#include "xgi_drm.h"
+
+struct xgi_aperture {
+ dma_addr_t base;
+ unsigned int size;
+};
+
+struct xgi_info {
+ struct drm_device *dev;
+
+ bool bootstrap_done;
+
+ /* physical characteristics */
+ struct xgi_aperture mmio;
+ struct xgi_aperture fb;
+ struct xgi_aperture pcie;
+
+ struct drm_map *mmio_map;
+ struct drm_map *pcie_map;
+ struct drm_map *fb_map;
+
+ /* look up table parameters */
+ struct drm_ati_pcigart_info gart_info;
+ unsigned int lutPageSize;
+
+ struct drm_sman sman;
+ bool fb_heap_initialized;
+ bool pcie_heap_initialized;
+
+ struct xgi_cmdring_info cmdring;
+
+ DRM_SPINTYPE fence_lock;
+ wait_queue_head_t fence_queue;
+ unsigned complete_sequence;
+ unsigned next_sequence;
+};
+
+extern long xgi_compat_ioctl(struct file *filp, unsigned int cmd,
+ unsigned long arg);
+
+extern int xgi_fb_heap_init(struct xgi_info * info);
+
+extern int xgi_alloc(struct xgi_info * info, struct xgi_mem_alloc * alloc,
+ struct drm_file * filp);
+
+extern int xgi_free(struct xgi_info * info, unsigned int index,
+ struct drm_file * filp);
+
+extern int xgi_pcie_heap_init(struct xgi_info * info);
+
+extern void *xgi_find_pcie_virt(struct xgi_info * info, u32 address);
+
+extern void xgi_enable_mmio(struct xgi_info * info);
+extern void xgi_disable_mmio(struct xgi_info * info);
+extern void xgi_enable_ge(struct xgi_info * info);
+extern void xgi_disable_ge(struct xgi_info * info);
+
+/* TTM-style fences.
+ */
+#ifdef XGI_HAVE_FENCE
+extern void xgi_poke_flush(struct drm_device * dev, uint32_t class);
+extern int xgi_fence_emit_sequence(struct drm_device * dev, uint32_t class,
+ uint32_t flags, uint32_t * sequence, uint32_t * native_type);
+extern void xgi_fence_handler(struct drm_device * dev);
+extern int xgi_fence_has_irq(struct drm_device *dev, uint32_t class,
+ uint32_t flags);
+#endif /* XGI_HAVE_FENCE */
+
+
+/* Non-TTM-style fences.
+ */
+extern int xgi_set_fence_ioctl(struct drm_device * dev, void * data,
+ struct drm_file * filp);
+extern int xgi_wait_fence_ioctl(struct drm_device * dev, void * data,
+ struct drm_file * filp);
+
+extern int xgi_alloc_ioctl(struct drm_device * dev, void * data,
+ struct drm_file * filp);
+extern int xgi_free_ioctl(struct drm_device * dev, void * data,
+ struct drm_file * filp);
+extern int xgi_submit_cmdlist(struct drm_device * dev, void * data,
+ struct drm_file * filp);
+extern int xgi_state_change_ioctl(struct drm_device * dev, void * data,
+ struct drm_file * filp);
+
+#endif
projects / platform / upstream / libdrm.git / blobdiff