#include <status_led.h>
#endif
#include <net.h>
+#include <serial.h>
#ifdef CFG_ALLOC_DPRAM
-#if !(defined(CONFIG_8260)||defined(CONFIG_MPC8560))
+#if !defined(CONFIG_CPM2)
#include <commproc.h>
#endif
#endif
board_early_init_f,
#endif
-#if !defined(CONFIG_TQM866M)
+#if !defined(CONFIG_8xx_CPUCLK_DEFAULT)
get_clocks, /* get CPU and bus clocks (etc.) */
#if defined(CONFIG_TQM8xxL) && !defined(CONFIG_TQM866M)
adjust_sdram_tbs_8xx,
init_timebase,
#endif
#ifdef CFG_ALLOC_DPRAM
-#if !(defined(CONFIG_8260) || defined(CONFIG_MPC8560))
+#if !defined(CONFIG_CPM2)
dpram_init,
#endif
#endif
board_postclk_init,
#endif
env_init,
-#if defined(CONFIG_TQM866M)
+#if defined(CONFIG_8xx_CPUCLK_DEFAULT)
get_clocks_866, /* get CPU and bus clocks according to the environment variable */
sdram_adjust_866, /* adjust sdram refresh rate according to the new clock */
init_timebase,
prt_8260_rsr,
prt_8260_clks,
#endif /* CONFIG_8260 */
+
+#if defined(CONFIG_MPC83XX)
+ print_clock_conf,
+#endif
+
checkcpu,
#if defined(CONFIG_MPC5xxx)
prt_mpc5xxx_clks,
#endif /* CONFIG_MPC5xxx */
+#if defined(CONFIG_MPC8220)
+ prt_mpc8220_clks,
+#endif
checkboard,
INIT_FUNC_WATCHDOG_INIT
#if defined(CONFIG_MISC_INIT_F)
/* compiler optimization barrier needed for GCC >= 3.4 */
__asm__ __volatile__("": : :"memory");
-#if !(defined(CONFIG_8260) || defined(CONFIG_MPC8560))
+#if !defined(CONFIG_CPM2)
/* Clear initial global data */
memset ((void *) gd, 0, sizeof (gd_t));
#endif
#ifdef CONFIG_IP860
bd->bi_sramstart = SRAM_BASE; /* start of SRAM memory */
bd->bi_sramsize = SRAM_SIZE; /* size of SRAM memory */
+#elif defined CONFIG_MPC8220
+ bd->bi_sramstart = CFG_SRAM_BASE; /* start of SRAM memory */
+ bd->bi_sramsize = CFG_SRAM_SIZE; /* size of SRAM memory */
#else
bd->bi_sramstart = 0; /* FIXME */ /* start of SRAM memory */
bd->bi_sramsize = 0; /* FIXME */ /* size of SRAM memory */
#if defined(CONFIG_MPC5xxx)
bd->bi_mbar_base = CFG_MBAR; /* base of internal registers */
#endif
+#if defined(CONFIG_MPC83XX)
+ bd->bi_immrbar = CFG_IMMRBAR;
+#endif
+#if defined(CONFIG_MPC8220)
+ bd->bi_mbar_base = CFG_MBAR; /* base of internal registers */
+ bd->bi_inpfreq = gd->inp_clk;
+ bd->bi_pcifreq = gd->pci_clk;
+ bd->bi_vcofreq = gd->vco_clk;
+ bd->bi_pevfreq = gd->pev_clk;
+ bd->bi_flbfreq = gd->flb_clk;
+
+ /* store bootparam to sram (backward compatible), here? */
+ {
+ u32 *sram = (u32 *)CFG_SRAM_BASE;
+ *sram++ = gd->ram_size;
+ *sram++ = gd->bus_clk;
+ *sram++ = gd->inp_clk;
+ *sram++ = gd->cpu_clk;
+ *sram++ = gd->vco_clk;
+ *sram++ = gd->flb_clk;
+ *sram++ = 0xb8c3ba11; /* boot signature */
+ }
+#endif
bd->bi_bootflags = bootflag; /* boot / reboot flag (for LynxOS) */
WATCHDOG_RESET ();
bd->bi_intfreq = gd->cpu_clk; /* Internal Freq, in Hz */
bd->bi_busfreq = gd->bus_clk; /* Bus Freq, in Hz */
-#if defined(CONFIG_8260) || defined(CONFIG_MPC8560)
+#if defined(CONFIG_CPM2)
bd->bi_cpmfreq = gd->cpm_clk;
bd->bi_brgfreq = gd->brg_clk;
bd->bi_sccfreq = gd->scc_clk;
bd->bi_vco = gd->vco_out;
-#endif /* CONFIG_8260 */
+#endif /* CONFIG_CPM2 */
#if defined(CONFIG_MPC5xxx)
bd->bi_ipbfreq = gd->ipb_clk;
bd->bi_pcifreq = gd->pci_clk;
bd->bi_procfreq = gd->cpu_clk; /* Processor Speed, In Hz */
bd->bi_plb_busfreq = gd->bus_clk;
-#if defined(CONFIG_405GP) || defined(CONFIG_405EP)
+#if defined(CONFIG_405GP) || defined(CONFIG_405EP) || defined(CONFIG_440_EP) || defined(CONFIG_440_GR)
bd->bi_pci_busfreq = get_PCI_freq ();
bd->bi_opbfreq = get_OPB_freq ();
#elif defined(CONFIG_XILINX_ML300)
monitor_flash_len = (ulong)&__init_end - dest_addr;
+#ifdef CONFIG_SERIAL_MULTI
+ serial_initialize();
+#endif
+
/*
* We have to relocate the command table manually
*/
load_sernum_ethaddr ();
#endif
-#if defined(CFG_GT_6426x) || defined(CONFIG_PN62) || defined(CONFIG_PPCHAMELEONEVB) || \
- defined(CONFIG_MPC8540ADS) || defined(CONFIG_MPC8560ADS) || defined(CONFIG_440_GX)
+#ifdef CONFIG_HAS_ETH1
/* handle the 2nd ethernet address */
s = getenv ("eth1addr");
s = (*e) ? e + 1 : e;
}
#endif
-#if defined(CFG_GT_6426x) || defined(CONFIG_MPC8540ADS) || defined(CONFIG_MPC8560ADS) || \
- defined(CONFIG_440_GX)
+#ifdef CONFIG_HAS_ETH2
/* handle the 3rd ethernet address */
s = getenv ("eth2addr");
}
#endif
-#if defined(CONFIG_440_GX)
+#ifdef CONFIG_HAS_ETH3
/* handle 4th ethernet address */
s = getenv("eth3addr");
#if defined(CONFIG_XPEDITE1K)
defined(CONFIG_IP860) || \
defined(CONFIG_IVML24) || \
defined(CONFIG_IVMS8) || \
- defined(CONFIG_LWMON) || \
defined(CONFIG_MPC8260ADS) || \
defined(CONFIG_MPC8266ADS) || \
defined(CONFIG_MPC8560ADS) || \
defined(CONFIG_PCU_E) || \
defined(CONFIG_RPXSUPER) || \
defined(CONFIG_STXGP3) || \
- defined(CONFIG_SPD823TS) )
+ defined(CONFIG_SPD823TS) || \
+ defined(CONFIG_RESET_PHY_R) )
WATCHDOG_RESET ();
debug ("Reset Ethernet PHY\n");
#if (CONFIG_COMMANDS & CFG_CMD_NAND)
WATCHDOG_RESET ();
- puts ("NAND:");
+ puts ("NAND: ");
nand_init(); /* go init the NAND */
#endif