armv8: fsl-layerscape: Support loading PPA header from eMMC/SD and NAND Flash

[platform/kernel/u-boot.git] / lib / fdtdec.c

diff --git a/lib/fdtdec.c b/lib/fdtdec.c
index 4e619c4..94372cc 100644 (file)
--- a/lib/fdtdec.c
+++ b/lib/fdtdec.c
@@ -66,6 +66,14 @@ static const char * const compat_names[COMPAT_COUNT] = {
        COMPAT(INTEL_BAYTRAIL_FSP_MDP, "intel,baytrail-fsp-mdp"),
        COMPAT(INTEL_IVYBRIDGE_FSP, "intel,ivybridge-fsp"),
        COMPAT(COMPAT_SUNXI_NAND, "allwinner,sun4i-a10-nand"),
+       COMPAT(ALTERA_SOCFPGA_CLK, "altr,clk-mgr"),
+       COMPAT(ALTERA_SOCFPGA_PINCTRL_SINGLE, "pinctrl-single"),
+       COMPAT(ALTERA_SOCFPGA_H2F_BRG, "altr,socfpga-hps2fpga-bridge"),
+       COMPAT(ALTERA_SOCFPGA_LWH2F_BRG, "altr,socfpga-lwhps2fpga-bridge"),
+       COMPAT(ALTERA_SOCFPGA_F2H_BRG, "altr,socfpga-fpga2hps-bridge"),
+       COMPAT(ALTERA_SOCFPGA_F2SDR0, "altr,socfpga-fpga2sdram0-bridge"),
+       COMPAT(ALTERA_SOCFPGA_F2SDR1, "altr,socfpga-fpga2sdram1-bridge"),
+       COMPAT(ALTERA_SOCFPGA_F2SDR2, "altr,socfpga-fpga2sdram2-bridge"),
 };
 
 const char *fdtdec_get_compatible(enum fdt_compat_id id)
@@ -112,7 +120,7 @@ fdt_addr_t fdtdec_get_addr_size_fixed(const void *blob, int node,
                return FDT_ADDR_T_NONE;
        }
 
-#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_OF_LIBFDT)
+#if CONFIG_IS_ENABLED(OF_TRANSLATE)
        if (translate)
                addr = fdt_translate_address(blob, node, prop_addr);
        else
@@ -1174,6 +1182,62 @@ int fdtdec_decode_display_timing(const void *blob, int parent, int index,
        return ret;
 }
 
+int fdtdec_setup_memory_size(void)
+{
+       int ret, mem;
+       struct fdt_resource res;
+
+       mem = fdt_path_offset(gd->fdt_blob, "/memory");
+       if (mem < 0) {
+               debug("%s: Missing /memory node\n", __func__);
+               return -EINVAL;
+       }
+
+       ret = fdt_get_resource(gd->fdt_blob, mem, "reg", 0, &res);
+       if (ret != 0) {
+               debug("%s: Unable to decode first memory bank\n", __func__);
+               return -EINVAL;
+       }
+
+       gd->ram_size = (phys_size_t)(res.end - res.start + 1);
+       debug("%s: Initial DRAM size %llx\n", __func__, (u64)gd->ram_size);
+
+       return 0;
+}
+
+#if defined(CONFIG_NR_DRAM_BANKS)
+int fdtdec_setup_memory_banksize(void)
+{
+       int bank, ret, mem;
+       struct fdt_resource res;
+
+       mem = fdt_path_offset(gd->fdt_blob, "/memory");
+       if (mem < 0) {
+               debug("%s: Missing /memory node\n", __func__);
+               return -EINVAL;
+       }
+
+       for (bank = 0; bank < CONFIG_NR_DRAM_BANKS; bank++) {
+               ret = fdt_get_resource(gd->fdt_blob, mem, "reg", bank, &res);
+               if (ret == -FDT_ERR_NOTFOUND)
+                       break;
+               if (ret != 0)
+                       return -EINVAL;
+
+               gd->bd->bi_dram[bank].start = (phys_addr_t)res.start;
+               gd->bd->bi_dram[bank].size =
+                       (phys_size_t)(res.end - res.start + 1);
+
+               debug("%s: DRAM Bank #%d: start = 0x%llx, size = 0x%llx\n",
+                     __func__, bank,
+                     (unsigned long long)gd->bd->bi_dram[bank].start,
+                     (unsigned long long)gd->bd->bi_dram[bank].size);
+       }
+
+       return 0;
+}
+#endif
+
 int fdtdec_setup(void)
 {
 #if CONFIG_IS_ENABLED(OF_CONTROL)