exynos: fix two warnings

[platform/upstream/libdrm.git] / intel / intel_decode.c

diff --git a/intel/intel_decode.c b/intel/intel_decode.c
index c9bfee4..61239dd 100644 (file)
--- a/intel/intel_decode.c
+++ b/intel/intel_decode.c
@@ -29,6 +29,7 @@
 #include <stdarg.h>
 #include <string.h>
 
+#include "xf86drm.h"
 #include "intel_chipset.h"
 #include "intel_bufmgr.h"
 
@@ -104,11 +105,7 @@ static float int_as_float(uint32_t intval)
        return uval.f;
 }
 
-static void
-instr_out(struct drm_intel_decode *ctx, unsigned int index,
-         const char *fmt, ...) __attribute__((format(__printf__, 3, 4)));
-
-static void
+static void DRM_PRINTFLIKE(3, 4)
 instr_out(struct drm_intel_decode *ctx, unsigned int index,
          const char *fmt, ...)
 {
@@ -139,6 +136,22 @@ instr_out(struct drm_intel_decode *ctx, unsigned int index,
 }
 
 static int
+decode_MI_SET_CONTEXT(struct drm_intel_decode *ctx)
+{
+       uint32_t data = ctx->data[1];
+       if (ctx->gen > 7)
+               return 1;
+
+       instr_out(ctx, 0, "MI_SET_CONTEXT\n");
+       instr_out(ctx, 1, "gtt offset = 0x%x%s%s\n",
+                 data & ~0xfff,
+                 data & (1<<1)? ", Force Restore": "",
+                 data & (1<<0)? ", Restore Inhibit": "");
+
+       return 2;
+}
+
+static int
 decode_MI_WAIT_FOR_EVENT(struct drm_intel_decode *ctx)
 {
        const char *cc_wait;
@@ -233,7 +246,7 @@ decode_mi(struct drm_intel_decode *ctx)
                { 0x00, 0, 1, 1, "MI_NOOP" },
                { 0x11, 0x3f, 2, 2, "MI_OVERLAY_FLIP" },
                { 0x07, 0, 1, 1, "MI_REPORT_HEAD" },
-               { 0x18, 0x3f, 2, 2, "MI_SET_CONTEXT" },
+               { 0x18, 0x3f, 2, 2, "MI_SET_CONTEXT", decode_MI_SET_CONTEXT },
                { 0x20, 0x3f, 3, 4, "MI_STORE_DATA_IMM" },
                { 0x21, 0x3f, 3, 4, "MI_STORE_DATA_INDEX" },
                { 0x24, 0x3f, 3, 3, "MI_STORE_REGISTER_MEM" },
@@ -241,6 +254,8 @@ decode_mi(struct drm_intel_decode *ctx)
                { 0x03, 0, 1, 1, "MI_WAIT_FOR_EVENT", decode_MI_WAIT_FOR_EVENT },
                { 0x16, 0x7f, 3, 3, "MI_SEMAPHORE_MBOX" },
                { 0x26, 0x1f, 3, 4, "MI_FLUSH_DW" },
+               { 0x28, 0x3f, 3, 3, "MI_REPORT_PERF_COUNT" },
+               { 0x29, 0xff, 3, 3, "MI_LOAD_REGISTER_MEM" },
                { 0x0b, 0, 1, 1, "MI_SUSPEND_FLUSH"},
        }, *opcode_mi = NULL;
 
@@ -1698,7 +1713,7 @@ decode_3d_1d(struct drm_intel_decode *ctx)
                                        }
                                } else {
                                        instr_out(ctx, i,
-                                                 "S%d: 0x%08x\n", i, data[i]);
+                                                 "S%d: 0x%08x\n", word, data[i]);
                                }
                                i++;
                        }
@@ -3146,7 +3161,7 @@ decode_3d_965(struct drm_intel_decode *ctx)
                { 0x7805, 0x00ff, 3, 3, "3DSTATE_URB" },
                { 0x7804, 0x00ff, 3, 3, "3DSTATE_CLEAR_PARAMS" },
                { 0x7806, 0x00ff, 3, 3, "3DSTATE_STENCIL_BUFFER" },
-               { 0x7807, 0x00ff, 4, 4, "3DSTATE_HIER_DEPTH_BUFFER", 6 },
+               { 0x790f, 0x00ff, 3, 3, "3DSTATE_HIER_DEPTH_BUFFER", 6 },
                { 0x7807, 0x00ff, 3, 3, "3DSTATE_HIER_DEPTH_BUFFER", 7, gen7_3DSTATE_HIER_DEPTH_BUFFER },
                { 0x7808, 0x00ff, 5, 257, "3DSTATE_VERTEX_BUFFERS" },
                { 0x7809, 0x00ff, 3, 256, "3DSTATE_VERTEX_ELEMENTS" },
@@ -3188,6 +3203,8 @@ decode_3d_965(struct drm_intel_decode *ctx)
                { 0x7829, 0x00ff, 2, 2, "3DSTATE_BINDING_TABLE_POINTERS_GS" },
                { 0x782a, 0x00ff, 2, 2, "3DSTATE_BINDING_TABLE_POINTERS_PS" },
                { 0x782b, 0x00ff, 2, 2, "3DSTATE_SAMPLER_STATE_POINTERS_VS" },
+               { 0x782c, 0x00ff, 2, 2, "3DSTATE_SAMPLER_STATE_POINTERS_HS" },
+               { 0x782d, 0x00ff, 2, 2, "3DSTATE_SAMPLER_STATE_POINTERS_DS" },
                { 0x782e, 0x00ff, 2, 2, "3DSTATE_SAMPLER_STATE_POINTERS_GS" },
                { 0x782f, 0x00ff, 2, 2, "3DSTATE_SAMPLER_STATE_POINTERS_PS" },
                { 0x7830, 0x00ff, 2, 2, NULL, 7, gen7_3DSTATE_URB_VS },
@@ -3206,7 +3223,7 @@ decode_3d_965(struct drm_intel_decode *ctx)
                { 0x790b, 0xffff, 4, 4, "3DSTATE_GS_SVB_INDEX" },
                { 0x790d, 0xffff, 3, 3, "3DSTATE_MULTISAMPLE", 6 },
                { 0x790d, 0xffff, 4, 4, "3DSTATE_MULTISAMPLE", 7 },
-               { 0x7910, 0xffff, 2, 2, "3DSTATE_CLEAR_PARAMS" },
+               { 0x7910, 0x00ff, 2, 2, "3DSTATE_CLEAR_PARAMS" },
                { 0x7912, 0x00ff, 2, 2, "3DSTATE_PUSH_CONSTANT_ALLOC_VS" },
                { 0x7913, 0x00ff, 2, 2, "3DSTATE_PUSH_CONSTANT_ALLOC_HS" },
                { 0x7914, 0x00ff, 2, 2, "3DSTATE_PUSH_CONSTANT_ALLOC_DS" },
@@ -3388,8 +3405,8 @@ decode_3d_965(struct drm_intel_decode *ctx)
                        instr_out(ctx, i,
                                  "buffer %d: %svalid, type 0x%04x, "
                                  "src offset 0x%04x bytes\n",
-                                 data[i] >> (IS_GEN6(devid) ? 26 : 27),
-                                 data[i] & (1 << (IS_GEN6(devid) ? 25 : 26)) ?
+                                 data[i] >> ((IS_GEN6(devid) || IS_GEN7(devid)) ? 26 : 27),
+                                 data[i] & (1 << ((IS_GEN6(devid) || IS_GEN7(devid)) ? 25 : 26)) ?
                                  "" : "in", (data[i] >> 16) & 0x1ff,
                                  data[i] & 0x07ff);
                        i++;
@@ -3807,7 +3824,9 @@ drm_intel_decode_context_alloc(uint32_t devid)
        ctx->devid = devid;
        ctx->out = stdout;
 
-       if (IS_GEN7(devid))
+       if (IS_GEN8(devid))
+               ctx->gen = 8;
+       else if (IS_GEN7(devid))
                ctx->gen = 7;
        else if (IS_GEN6(devid))
                ctx->gen = 6;