PM_API_MAX,
};
+enum pm_node_id {
+ NODE_UNKNOWN = 0,
+ NODE_APU = 1,
+ NODE_APU_0 = 2,
+ NODE_APU_1 = 3,
+ NODE_APU_2 = 4,
+ NODE_APU_3 = 5,
+ NODE_RPU = 6,
+ NODE_RPU_0 = 7,
+ NODE_RPU_1 = 8,
+ NODE_PLD = 9,
+ NODE_FPD = 10,
+ NODE_OCM_BANK_0 = 11,
+ NODE_OCM_BANK_1 = 12,
+ NODE_OCM_BANK_2 = 13,
+ NODE_OCM_BANK_3 = 14,
+ NODE_TCM_0_A = 15,
+ NODE_TCM_0_B = 16,
+ NODE_TCM_1_A = 17,
+ NODE_TCM_1_B = 18,
+ NODE_L2 = 19,
+ NODE_GPU_PP_0 = 20,
+ NODE_GPU_PP_1 = 21,
+ NODE_USB_0 = 22,
+ NODE_USB_1 = 23,
+ NODE_TTC_0 = 24,
+ NODE_TTC_1 = 25,
+ NODE_TTC_2 = 26,
+ NODE_TTC_3 = 27,
+ NODE_SATA = 28,
+ NODE_ETH_0 = 29,
+ NODE_ETH_1 = 30,
+ NODE_ETH_2 = 31,
+ NODE_ETH_3 = 32,
+ NODE_UART_0 = 33,
+ NODE_UART_1 = 34,
+ NODE_SPI_0 = 35,
+ NODE_SPI_1 = 36,
+ NODE_I2C_0 = 37,
+ NODE_I2C_1 = 38,
+ NODE_SD_0 = 39,
+ NODE_SD_1 = 40,
+ NODE_DP = 41,
+ NODE_GDMA = 42,
+ NODE_ADMA = 43,
+ NODE_NAND = 44,
+ NODE_QSPI = 45,
+ NODE_GPIO = 46,
+ NODE_CAN_0 = 47,
+ NODE_CAN_1 = 48,
+ NODE_EXTERN = 49,
+ NODE_APLL = 50,
+ NODE_VPLL = 51,
+ NODE_DPLL = 52,
+ NODE_RPLL = 53,
+ NODE_IOPLL = 54,
+ NODE_DDR = 55,
+ NODE_IPI_APU = 56,
+ NODE_IPI_RPU_0 = 57,
+ NODE_GPU = 58,
+ NODE_PCIE = 59,
+ NODE_PCAP = 60,
+ NODE_RTC = 61,
+ NODE_LPD = 62,
+ NODE_VCU = 63,
+ NODE_IPI_RPU_1 = 64,
+ NODE_IPI_PL_0 = 65,
+ NODE_IPI_PL_1 = 66,
+ NODE_IPI_PL_2 = 67,
+ NODE_IPI_PL_3 = 68,
+ NODE_PL = 69,
+ NODE_GEM_TSU = 70,
+ NODE_SWDT_0 = 71,
+ NODE_SWDT_1 = 72,
+ NODE_CSU = 73,
+ NODE_PJTAG = 74,
+ NODE_TRACE = 75,
+ NODE_TESTSCAN = 76,
+ NODE_PMU = 77,
+ NODE_MAX = 78,
+};
+
+enum tap_delay_type {
+ PM_TAPDELAY_INPUT = 0,
+ PM_TAPDELAY_OUTPUT = 1,
+};
+
+enum dll_reset_type {
+ PM_DLL_RESET_ASSERT = 0,
+ PM_DLL_RESET_RELEASE = 1,
+ PM_DLL_RESET_PULSE = 2,
+};
+
+enum ospi_mux_select_type {
+ PM_OSPI_MUX_SEL_DMA,
+ PM_OSPI_MUX_SEL_LINEAR,
+ PM_OSPI_MUX_GET_MODE,
+};
+
enum pm_query_id {
PM_QID_INVALID = 0,
PM_QID_CLOCK_GET_NAME = 1,
PM_QID_CLOCK_GET_MAX_DIVISOR = 13,
};
+enum pm_pinctrl_config_param {
+ PM_PINCTRL_CONFIG_SLEW_RATE = 0,
+ PM_PINCTRL_CONFIG_BIAS_STATUS = 1,
+ PM_PINCTRL_CONFIG_PULL_CTRL = 2,
+ PM_PINCTRL_CONFIG_SCHMITT_CMOS = 3,
+ PM_PINCTRL_CONFIG_DRIVE_STRENGTH = 4,
+ PM_PINCTRL_CONFIG_VOLTAGE_STATUS = 5,
+ PM_PINCTRL_CONFIG_TRI_STATE = 6,
+ PM_PINCTRL_CONFIG_MAX = 7,
+};
+
+enum pm_pinctrl_slew_rate {
+ PM_PINCTRL_SLEW_RATE_FAST = 0,
+ PM_PINCTRL_SLEW_RATE_SLOW = 1,
+};
+
+enum pm_pinctrl_bias_status {
+ PM_PINCTRL_BIAS_DISABLE = 0,
+ PM_PINCTRL_BIAS_ENABLE = 1,
+};
+
+enum pm_pinctrl_pull_ctrl {
+ PM_PINCTRL_BIAS_PULL_DOWN = 0,
+ PM_PINCTRL_BIAS_PULL_UP = 1,
+};
+
+enum pm_pinctrl_schmitt_cmos {
+ PM_PINCTRL_INPUT_TYPE_CMOS = 0,
+ PM_PINCTRL_INPUT_TYPE_SCHMITT = 1,
+};
+
+enum pm_pinctrl_drive_strength {
+ PM_PINCTRL_DRIVE_STRENGTH_2MA = 0,
+ PM_PINCTRL_DRIVE_STRENGTH_4MA = 1,
+ PM_PINCTRL_DRIVE_STRENGTH_8MA = 2,
+ PM_PINCTRL_DRIVE_STRENGTH_12MA = 3,
+};
+
+enum pm_pinctrl_tri_state {
+ PM_PINCTRL_TRI_STATE_DISABLE = 0,
+ PM_PINCTRL_TRI_STATE_ENABLE = 1,
+};
+
enum zynqmp_pm_reset_action {
PM_RESET_ACTION_RELEASE = 0,
PM_RESET_ACTION_ASSERT = 1,
ZYNQMP_PM_RESET_END = ZYNQMP_PM_RESET_PS_PL3
};
-#define PM_SIP_SVC 0xc2000000
+enum pm_ioctl_id {
+ IOCTL_GET_RPU_OPER_MODE = 0,
+ IOCTL_SET_RPU_OPER_MODE = 1,
+ IOCTL_RPU_BOOT_ADDR_CONFIG = 2,
+ IOCTL_TCM_COMB_CONFIG = 3,
+ IOCTL_SET_TAPDELAY_BYPASS = 4,
+ IOCTL_SET_SGMII_MODE = 5,
+ IOCTL_SD_DLL_RESET = 6,
+ IOCTL_SET_SD_TAPDELAY = 7,
+ IOCTL_SET_PLL_FRAC_MODE = 8,
+ IOCTL_GET_PLL_FRAC_MODE = 9,
+ IOCTL_SET_PLL_FRAC_DATA = 10,
+ IOCTL_GET_PLL_FRAC_DATA = 11,
+ IOCTL_WRITE_GGS = 12,
+ IOCTL_READ_GGS = 13,
+ IOCTL_WRITE_PGGS = 14,
+ IOCTL_READ_PGGS = 15,
+ /* IOCTL for ULPI reset */
+ IOCTL_ULPI_RESET = 16,
+ /* Set healthy bit value*/
+ IOCTL_SET_BOOT_HEALTH_STATUS = 17,
+ IOCTL_AFI = 18,
+ /* Probe counter read/write */
+ IOCTL_PROBE_COUNTER_READ = 19,
+ IOCTL_PROBE_COUNTER_WRITE = 20,
+ IOCTL_OSPI_MUX_SELECT = 21,
+ /* IOCTL for USB power request */
+ IOCTL_USB_SET_STATE = 22,
+ /* IOCTL to get last reset reason */
+ IOCTL_GET_LAST_RESET_REASON = 23,
+ /* AIE ISR Clear */
+ IOCTL_AIE_ISR_CLEAR = 24,
+ /* Register SGI to ATF */
+ IOCTL_REGISTER_SGI = 25,
+ /* Runtime feature configuration */
+ IOCTL_SET_FEATURE_CONFIG = 26,
+ IOCTL_GET_FEATURE_CONFIG = 27,
+ /* IOCTL for Secure Read/Write Interface */
+ IOCTL_READ_REG = 28,
+ IOCTL_MASK_WRITE_REG = 29,
+ /* Dynamic SD/GEM/USB configuration */
+ IOCTL_SET_SD_CONFIG = 30,
+ IOCTL_SET_GEM_CONFIG = 31,
+ IOCTL_SET_USB_CONFIG = 32,
+ /* AIE/AIEML Operations */
+ IOCTL_AIE_OPS = 33,
+ /* IOCTL to get default/current QoS */
+ IOCTL_GET_QOS = 34,
+};
+
+enum pm_sd_config_type {
+ SD_CONFIG_EMMC_SEL = 1, /* To set SD_EMMC_SEL in CTRL_REG_SD */
+ SD_CONFIG_BASECLK = 2, /* To set SD_BASECLK in SD_CONFIG_REG1 */
+ SD_CONFIG_8BIT = 3, /* To set SD_8BIT in SD_CONFIG_REG2 */
+ SD_CONFIG_FIXED = 4, /* To set fixed config registers */
+};
+
+enum pm_gem_config_type {
+ GEM_CONFIG_SGMII_MODE = 1, /* To set GEM_SGMII_MODE in GEM_CLK_CTRL */
+ GEM_CONFIG_FIXED = 2, /* To set fixed config registers */
+};
-#define ZYNQMP_PM_VERSION_MAJOR 1
-#define ZYNQMP_PM_VERSION_MINOR 0
-#define ZYNQMP_PM_VERSION_MAJOR_SHIFT 16
-#define ZYNQMP_PM_VERSION_MINOR_MASK 0xFFFF
+#define PM_SIP_SVC 0xc2000000
+
+#define ZYNQMP_PM_VERSION_MAJOR 1
+#define ZYNQMP_PM_VERSION_MINOR 0
+#define ZYNQMP_PM_VERSION_MAJOR_SHIFT 16
+#define ZYNQMP_PM_VERSION_MINOR_MASK 0xFFFF
#define ZYNQMP_PM_VERSION \
((ZYNQMP_PM_VERSION_MAJOR << ZYNQMP_PM_VERSION_MAJOR_SHIFT) | \
ZYNQMP_PM_VERSION_MINOR)
-#define ZYNQMP_PM_VERSION_INVALID ~0
+#define ZYNQMP_PM_VERSION_INVALID ~0
-#define PMUFW_V1_0 ((1 << ZYNQMP_PM_VERSION_MAJOR_SHIFT) | 0)
+#define PMUFW_V1_0 ((1 << ZYNQMP_PM_VERSION_MAJOR_SHIFT) | 0)
+#define PMIO_NODE_ID_BASE 0x1410801B
/*
* Return payload size
#define PAYLOAD_ARG_CNT 5U
unsigned int zynqmp_firmware_version(void);
-void zynqmp_pmufw_load_config_object(const void *cfg_obj, size_t size);
+int zynqmp_pmufw_node(u32 id);
+int zynqmp_pmufw_config_close(void);
+int zynqmp_pmufw_load_config_object(const void *cfg_obj, size_t size);
int xilinx_pm_request(u32 api_id, u32 arg0, u32 arg1, u32 arg2,
u32 arg3, u32 *ret_payload);
+int zynqmp_pm_set_sd_config(u32 node, enum pm_sd_config_type config, u32 value);
+int zynqmp_pm_set_gem_config(u32 node, enum pm_gem_config_type config,
+ u32 value);
+int zynqmp_pm_is_function_supported(const u32 api_id, const u32 id);
+
+/* Type of Config Object */
+#define PM_CONFIG_OBJECT_TYPE_BASE 0x1U
+#define PM_CONFIG_OBJECT_TYPE_OVERLAY 0x2U
+
+/* Section Id */
+#define PM_CONFIG_SLAVE_SECTION_ID 0x102U
+#define PM_CONFIG_SET_CONFIG_SECTION_ID 0x107U
+
+/* Flag Option */
+#define PM_SLAVE_FLAG_IS_SHAREABLE 0x1U
+#define PM_MASTER_USING_SLAVE_MASK 0x2U
+
+/* IPI Mask for Master */
+#define PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK 0x00000001
+#define PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK 0x00000100
+#define PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK 0x00000200
+
+enum zynqmp_pm_request_ack {
+ ZYNQMP_PM_REQUEST_ACK_NO = 1,
+ ZYNQMP_PM_REQUEST_ACK_BLOCKING = 2,
+ ZYNQMP_PM_REQUEST_ACK_NON_BLOCKING = 3,
+};
+
+/* Node capabilities */
+#define ZYNQMP_PM_CAPABILITY_ACCESS 0x1U
+#define ZYNQMP_PM_CAPABILITY_CONTEXT 0x2U
+#define ZYNQMP_PM_CAPABILITY_WAKEUP 0x4U
+#define ZYNQMP_PM_CAPABILITY_UNUSABLE 0x8U
+
+#define ZYNQMP_PM_MAX_QOS 100U
+/* Firmware feature check version mask */
+#define FIRMWARE_VERSION_MASK GENMASK(15, 0)
+/* PM API versions */
+#define PM_API_VERSION_2 2
+
+struct zynqmp_ipi_msg {
+ size_t len;
+ u32 *buf;
+};
#endif /* _ZYNQMP_FIRMWARE_H_ */