#define VSC9953_PORT_CFG_LEARN_AUTO 0x00000100
#define VSC9953_PORT_CFG_LEARN_CPU 0x00000200
#define VSC9953_PORT_CFG_LEARN_DROP 0x00000400
+#define VSC9953_PORT_CFG_PORTID_MASK 0x0000003c
/* Macros for vsc9953_qsys_sys.switch_port_mode register */
#define VSC9953_PORT_ENA 0x00002000
/* Macros for vsc9953_ana_ana_tables.mach_data register */
#define VSC9953_MACHDATA_VID_MASK 0x1fff0000
+/* Macros for vsc9953_ana_common.aggr_cfg register */
+#define VSC9953_AC_RND_ENA 0x00000080
+#define VSC9953_AC_DMAC_ENA 0x00000040
+#define VSC9953_AC_SMAC_ENA 0x00000020
+#define VSC9953_AC_IP6_LBL_ENA 0x00000010
+#define VSC9953_AC_IP6_TCPUDP_ENA 0x00000008
+#define VSC9953_AC_IP4_SIPDIP_ENA 0x00000004
+#define VSC9953_AC_IP4_TCPUDP_ENA 0x00000002
+#define VSC9953_AC_MASK 0x000000fe
+
+/* Macros for vsc9953_ana_pgid.port_grp_id[] registers */
+#define VSC9953_PGID_PORT_MASK 0x000003ff
+
#define VSC9953_MAX_PORTS 10
#define VSC9953_PORT_CHECK(port) \
(((port) < 0 || (port) >= VSC9953_MAX_PORTS) ? 0 : 1)
u32 port_mode[12];
};
+#define PGID_DST_START 0
+#define PGID_AGGR_START 64
+#define PGID_SRC_START 80
+
struct vsc9953_ana_pgid {
u32 port_grp_id[91];
};