SANDBOX_CLK_ECSPI1,
SANDBOX_CLK_USDHC1_SEL,
SANDBOX_CLK_USDHC2_SEL,
+ SANDBOX_CLK_I2C,
+ SANDBOX_CLK_I2C_ROOT,
};
enum sandbox_pllv3_type {
reg, shift, width, 0);
}
+static inline struct clk *sandbox_clk_gate(const char *name, const char *parent,
+ void __iomem *reg, u8 bit_idx,
+ u8 clk_gate_flags)
+{
+ return clk_register_gate(NULL, name, parent, CLK_SET_RATE_PARENT,
+ reg, bit_idx, clk_gate_flags, NULL);
+}
+
struct clk *sandbox_clk_register_gate2(struct device *dev, const char *name,
const char *parent_name,
unsigned long flags,
width, 0);
}
+int sandbox_clk_enable_count(struct clk *clk);
+
#endif /* __SANDBOX_CLK_H__ */