#define ivor13 0x19d /* interrupt vector offset register 13 */
#define ivor14 0x19e /* interrupt vector offset register 14 */
#define ivor15 0x19f /* interrupt vector offset register 15 */
-#if defined(CONFIG_440GX) || \
- defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
- defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
- defined(CONFIG_440SP) || defined(CONFIG_440SPE)
+#if defined(CONFIG_440)
#define mcsrr0 0x23a /* machine check save/restore register 0 */
#define mcsrr1 0x23b /* mahcine check save/restore register 1 */
#define mcsr 0x23c /* machine check status register */
#define icdbtrh 0x39f /* instruction cache debug tag register high */
#define mmucr 0x3b2 /* mmu control register */
#define ccr0 0x3b3 /* core configuration register 0 */
-#define ccr1 0x378 /* core configuration for 440x5 only */
+#define ccr1 0x378 /* core configuration for 440x5 only */
#define icdbdr 0x3d3 /* instruction cache debug data register */
#define dbdr 0x3f3 /* debug data register */
#define clk_opbd 0x00c0
#define clk_perd 0x00e0
#define clk_mald 0x0100
-#define clk_spcid 0x0120
+#define clk_spcid 0x0120
#define clk_icfg 0x0140
/* 440gx sdr register definations */
#define sdrcfgd (SDR_DCR_BASE+0x1)
#define sdr_sdstp0 0x0020 /* */
#define sdr_sdstp1 0x0021 /* */
-#define sdr_pinstp 0x0040
+#define SDR_PINSTP 0x0040
#define sdr_sdcs 0x0060
#define sdr_ecid0 0x0080
#define sdr_ecid1 0x0081
#define sdr_sdstp3 0x4003
#endif /* CONFIG_440GX */
+/*----------------------------------------------------------------------------+
+| Core Configuration/MMU configuration for 440 (CCR1 for 440x5 only).
++----------------------------------------------------------------------------*/
+#define CCR0_PRE 0x40000000
+#define CCR0_CRPE 0x08000000
+#define CCR0_DSTG 0x00200000
+#define CCR0_DAPUIB 0x00100000
+#define CCR0_DTB 0x00008000
+#define CCR0_GICBT 0x00004000
+#define CCR0_GDCBT 0x00002000
+#define CCR0_FLSTA 0x00000100
+#define CCR0_ICSLC_MASK 0x0000000C
+#define CCR0_ICSLT_MASK 0x00000003
+#define CCR1_TCS_MASK 0x00000080
+#define CCR1_TCS_INTCLK 0x00000000
+#define CCR1_TCS_EXTCLK 0x00000080
+#define MMUCR_SWOA 0x01000000
+#define MMUCR_U1TE 0x00400000
+#define MMUCR_U2SWOAE 0x00200000
+#define MMUCR_DULXE 0x00800000
+#define MMUCR_IULXE 0x00400000
+#define MMUCR_STS 0x00100000
+#define MMUCR_STID_MASK 0x000000FF
+
#ifdef CONFIG_440SPE
#undef sdr_sdstp2
#define sdr_sdstp2 0x0022
#define sdr_sdstp6 0x4005
#define sdr_sdstp7 0x4007
-/*----------------------------------------------------------------------------+
-| Core Configuration/MMU configuration for 440 (CCR1 for 440x5 only).
-+----------------------------------------------------------------------------*/
-#define CCR0_PRE 0x40000000
-#define CCR0_CRPE 0x08000000
-#define CCR0_DSTG 0x00200000
-#define CCR0_DAPUIB 0x00100000
-#define CCR0_DTB 0x00008000
-#define CCR0_GICBT 0x00004000
-#define CCR0_GDCBT 0x00002000
-#define CCR0_FLSTA 0x00000100
-#define CCR0_ICSLC_MASK 0x0000000C
-#define CCR0_ICSLT_MASK 0x00000003
-#define CCR1_TCS_MASK 0x00000080
-#define CCR1_TCS_INTCLK 0x00000000
-#define CCR1_TCS_EXTCLK 0x00000080
-#define MMUCR_SEOA 0x01000000
-#define MMUCR_U1TE 0x00400000
-#define MMUCR_U2SWOAE 0x00200000
-#define MMUCR_DULXE 0x00800000
-#define MMUCR_IULXE 0x00400000
-#define MMUCR_STS 0x00100000
-#define MMUCR_STID_MASK 0x000000FF
-
#define SDR0_CFGADDR 0x00E
#define SDR0_CFGDATA 0x00F
#define SDR0_PEGPLLSET1 0x000003A0 /* PE Pll LC Tank Setting1 */
#define SDR0_PEGPLLSET2 0x000003A1 /* PE Pll LC Tank Setting2 */
#define SDR0_PEGPLLSTS 0x000003A2 /* PE Pll LC Tank Status */
+#endif /* CONFIG_440SPE */
+#if defined(CONFIG_440SP) || defined(CONFIG_440SPE)
/*----------------------------------------------------------------------------+
| SDRAM Controller
+----------------------------------------------------------------------------*/
/*-----------------------------------------------------------------------------+
| Memory Bank 0-7 configuration
+-----------------------------------------------------------------------------*/
-#define SDRAM_RXBAS_SDBA_MASK 0xFF800000 /* Base address */
+#if defined(CONFIG_440SPE)
+#define SDRAM_RXBAS_SDBA_MASK 0xFFE00000 /* Base address */
#define SDRAM_RXBAS_SDBA_ENCODE(n) ((((unsigned long)(n))&0xFFE00000)>>2)
#define SDRAM_RXBAS_SDBA_DECODE(n) ((((unsigned long)(n))&0xFFE00000)<<2)
+#endif /* CONFIG_440SPE */
+#if defined(CONFIG_440SP)
+#define SDRAM_RXBAS_SDBA_MASK 0xFF800000 /* Base address */
+#define SDRAM_RXBAS_SDBA_ENCODE(n) ((((unsigned long)(n))&0xFF800000))
+#define SDRAM_RXBAS_SDBA_DECODE(n) ((((unsigned long)(n))&0xFF800000))
+#endif /* CONFIG_440SP */
#define SDRAM_RXBAS_SDSZ_MASK 0x0000FFC0 /* Size */
#define SDRAM_RXBAS_SDSZ_ENCODE(n) ((((unsigned long)(n))&0x3FF)<<6)
#define SDRAM_RXBAS_SDSZ_DECODE(n) ((((unsigned long)(n))>>6)&0x3FF)
#define SDRAM_MCSTAT_MIC_MASK 0x80000000 /* Memory init status mask */
#define SDRAM_MCSTAT_MIC_NOTCOMP 0x00000000 /* Mem init not complete */
#define SDRAM_MCSTAT_MIC_COMP 0x80000000 /* Mem init complete */
-#define SDRAM_MCSTAT_SRMS_MASK 0x80000000 /* Mem self refresh stat mask */
+#define SDRAM_MCSTAT_SRMS_MASK 0x40000000 /* Mem self refresh stat mask */
#define SDRAM_MCSTAT_SRMS_NOT_SF 0x00000000 /* Mem not in self refresh */
-#define SDRAM_MCSTAT_SRMS_SF 0x80000000 /* Mem in self refresh */
+#define SDRAM_MCSTAT_SRMS_SF 0x40000000 /* Mem in self refresh */
+#define SDRAM_MCSTAT_IDLE_MASK 0x20000000 /* Mem self refresh stat mask */
+#define SDRAM_MCSTAT_IDLE_NOT 0x00000000 /* Mem contr not idle */
+#define SDRAM_MCSTAT_IDLE 0x20000000 /* Mem contr idle */
/*-----------------------------------------------------------------------------+
| Memory Controller Options 1
#define SDRAM_CODT_CKSE_SINGLE_END 0x00000008
#define SDRAM_CODT_FEEBBACK_RCV_SINGLE_END 0x00000004
#define SDRAM_CODT_FEEBBACK_DRV_SINGLE_END 0x00000002
-#define SDRAM_CODT_IO_HIZ 0x00000000
-#define SDRAM_CODT_IO_NMODE 0x00000001
+#define SDRAM_CODT_IO_HIZ 0x00000000
+#define SDRAM_CODT_IO_NMODE 0x00000001
/*-----------------------------------------------------------------------------+
| SDRAM Mode Register
#define SDRAM_WRDTR_LLWP_1_CYC 0x00000000
#define SDRAM_WRDTR_WTR_MASK 0x0E000000
#define SDRAM_WRDTR_WTR_0_DEG 0x06000000
+#define SDRAM_WRDTR_WTR_90_DEG_ADV 0x04000000
#define SDRAM_WRDTR_WTR_180_DEG_ADV 0x02000000
#define SDRAM_WRDTR_WTR_270_DEG_ADV 0x00000000
#define pbear 0x20 /* periph bus error addr reg */
#define pbesr 0x21 /* periph bus error status reg */
#define xbcfg 0x23 /* external bus configuration reg */
+#define EBC0_CFG 0x23 /* external bus configuration reg */
#define xbcid 0x24 /* external bus core id reg */
#if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
/* PLB4 Arbiter - PowerPC440EP Pass1 */
#define PLB4_DCR_BASE 0x080
+#define plb4_acr (PLB4_DCR_BASE+0x1)
#define plb4_revid (PLB4_DCR_BASE+0x2)
-#define plb4_acr (PLB4_DCR_BASE+0x3)
#define plb4_besr (PLB4_DCR_BASE+0x4)
#define plb4_bearl (PLB4_DCR_BASE+0x6)
#define plb4_bearh (PLB4_DCR_BASE+0x7)
+#define PLB4_ACR_WRP (0x80000000 >> 7)
+
/* Nebula PLB4 Arbiter - PowerPC440EP */
#define PLB_ARBITER_BASE 0x80
#define plb1_bearl (PLB_ARBITER_BASE+ 0x0C)
#define plb1_bearh (PLB_ARBITER_BASE+ 0x0D)
-#if defined(CONFIG_440EP) || defined(CONFIG_440GR)
+#if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
+ defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
/* Pin Function Control Register 1 */
#define SDR0_PFC1 0x4101
#define SDR0_PFC1_U1ME_MASK 0x02000000 /* UART1 Mode Enable */
#endif /* defined(CONFIG_440EP) || defined(CONFIG_440GR) */
#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
-#define SDR_USB2D0CR 0x0320
+#define SDR0_USB2D0CR 0x0320
#define SDR0_USB2D0CR_USB2DEV_EBC_SEL_MASK 0x00000004 /* USB 2.0 Device/EBC Master Selection */
#define SDR0_USB2D0CR_USB2DEV_SELECTION 0x00000004 /* USB 2.0 Device Selection */
#define SDR0_USB2D0CR_EBC_SELECTION 0x00000000 /* EBC Selection */
#define SDR0_PFC2_SELECT_CONFIG_5 0xC0000000 /* 2xRTBI using RGMII bridge */
#define SDR0_PFC2_SELECT_CONFIG_6 0x40000000 /* 2xSMII using ZMII bridge */
+#define SDR0_PFC4 0x4104
+
/* USB2PHY0 Control Register */
#define SDR0_USB2PHY0CR 0x4103
#define SDR0_USB2PHY0CR_UTMICN_MASK 0x00100000 /* PHY UTMI interface connection */
#if defined(CONFIG_440SPE) || defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
#define UIC2_DCR_BASE 0xe0
-#define uic2sr (UIC0_DCR_BASE+0x0) /* UIC2 status-Read Clear */
-#define uic2srs (UIC0_DCR_BASE+0x1) /* UIC2 status-Read Set */
-#define uic2er (UIC0_DCR_BASE+0x2) /* UIC2 enable */
-#define uic2cr (UIC0_DCR_BASE+0x3) /* UIC2 critical */
-#define uic2pr (UIC0_DCR_BASE+0x4) /* UIC2 polarity */
-#define uic2tr (UIC0_DCR_BASE+0x5) /* UIC2 triggering */
-#define uic2msr (UIC0_DCR_BASE+0x6) /* UIC2 masked status */
-#define uic2vr (UIC0_DCR_BASE+0x7) /* UIC2 vector */
-#define uic2vcr (UIC0_DCR_BASE+0x8) /* UIC2 vector configuration */
+#define uic2sr (UIC2_DCR_BASE+0x0) /* UIC2 status-Read Clear */
+#define uic2srs (UIC2_DCR_BASE+0x1) /* UIC2 status-Read Set */
+#define uic2er (UIC2_DCR_BASE+0x2) /* UIC2 enable */
+#define uic2cr (UIC2_DCR_BASE+0x3) /* UIC2 critical */
+#define uic2pr (UIC2_DCR_BASE+0x4) /* UIC2 polarity */
+#define uic2tr (UIC2_DCR_BASE+0x5) /* UIC2 triggering */
+#define uic2msr (UIC2_DCR_BASE+0x6) /* UIC2 masked status */
+#define uic2vr (UIC2_DCR_BASE+0x7) /* UIC2 vector */
+#define uic2vcr (UIC2_DCR_BASE+0x8) /* UIC2 vector configuration */
#define UIC3_DCR_BASE 0xf0
-#define uic3sr (UIC1_DCR_BASE+0x0) /* UIC3 status-Read Clear */
-#define uic3srs (UIC0_DCR_BASE+0x1) /* UIC3 status-Read Set */
-#define uic3er (UIC1_DCR_BASE+0x2) /* UIC3 enable */
-#define uic3cr (UIC1_DCR_BASE+0x3) /* UIC3 critical */
-#define uic3pr (UIC1_DCR_BASE+0x4) /* UIC3 polarity */
-#define uic3tr (UIC1_DCR_BASE+0x5) /* UIC3 triggering */
-#define uic3msr (UIC1_DCR_BASE+0x6) /* UIC3 masked status */
-#define uic3vr (UIC1_DCR_BASE+0x7) /* UIC3 vector */
-#define uic3vcr (UIC1_DCR_BASE+0x8) /* UIC3 vector configuration */
+#define uic3sr (UIC3_DCR_BASE+0x0) /* UIC3 status-Read Clear */
+#define uic3srs (UIC3_DCR_BASE+0x1) /* UIC3 status-Read Set */
+#define uic3er (UIC3_DCR_BASE+0x2) /* UIC3 enable */
+#define uic3cr (UIC3_DCR_BASE+0x3) /* UIC3 critical */
+#define uic3pr (UIC3_DCR_BASE+0x4) /* UIC3 polarity */
+#define uic3tr (UIC3_DCR_BASE+0x5) /* UIC3 triggering */
+#define uic3msr (UIC3_DCR_BASE+0x6) /* UIC3 masked status */
+#define uic3vr (UIC3_DCR_BASE+0x7) /* UIC3 vector */
+#define uic3vcr (UIC3_DCR_BASE+0x8) /* UIC3 vector configuration */
#endif /* CONFIG_440SPE */
#if defined(CONFIG_440GX)
#define uicvr uic0vr
#define uicvcr uic0vcr
-#if defined(CONFIG_440SPE)
+#if defined(CONFIG_440SPE) || defined(CONFIG_440EPX)
/*----------------------------------------------------------------------------+
| Clock / Power-on-reset DCR's.
+----------------------------------------------------------------------------*/
-#define CPR0_CFGADDR 0x00C
-#define CPR0_CFGDATA 0x00D
-
#define CPR0_CLKUPD 0x20
#define CPR0_CLKUPD_BSY_MASK 0x80000000
#define CPR0_CLKUPD_BSY_COMPLETED 0x00000000
#define CPR0_OPBD_OPBDV0_DECODE(n) ((((((unsigned long)(n))>>24)-1)&0x03)+1)
#define CPR0_PERD 0xE0
+#if !defined(CONFIG_440EPX)
#define CPR0_PERD_PERDV0_MASK 0x03000000
#define CPR0_PERD_PERDV0_ENCODE(n) ((((unsigned long)(n))&0x03)<<24)
#define CPR0_PERD_PERDV0_DECODE(n) ((((((unsigned long)(n))>>24)-1)&0x03)+1)
+#endif
#define CPR0_MALD 0x100
#define CPR0_MALD_MALDV0_MASK 0x03000000
/*-----------------------------------------------------------------------------+
| SDR0 Bit Settings
+-----------------------------------------------------------------------------*/
+#if defined(CONFIG_440SP)
+#define SDR0_SRST 0x0200
+
+#define SDR0_DDR0 0x00E1
+#define SDR0_DDR0_DPLLRST 0x80000000
+#define SDR0_DDR0_DDRM_MASK 0x60000000
+#define SDR0_DDR0_DDRM_DDR1 0x20000000
+#define SDR0_DDR0_DDRM_DDR2 0x40000000
+#define SDR0_DDR0_DDRM_ENCODE(n) ((((unsigned long)(n))&0x03)<<29)
+#define SDR0_DDR0_DDRM_DECODE(n) ((((unsigned long)(n))>>29)&0x03)
+#define SDR0_DDR0_TUNE_ENCODE(n) ((((unsigned long)(n))&0x2FF)<<0)
+#define SDR0_DDR0_TUNE_DECODE(n) ((((unsigned long)(n))>>0)&0x2FF)
+#endif
+
#if defined(CONFIG_440SPE)
#define SDR0_CP440 0x0180
#define SDR0_CP440_ERPN_MASK 0x30000000
#define GPIO0 0
#define GPIO1 1
-#if defined(CONFIG_440GP)
+#if defined(CONFIG_440GP) || defined(CONFIG_440GX) || \
+ defined(CONFIG_440SP) || defined(CONFIG_440SPE)
#define GPIO0_BASE (CFG_PERIPHERAL_BASE+0x00000700)
#define GPIO0_OR (GPIO0_BASE+0x0)
#define GPIO1_ISR3H (GPIO1_BASE+0x44)
#endif
-#define GPIO_GROUP_MAX 2
-#define GPIO_MAX 32
-#define GPIO_ALT1_SEL 0x40000000 /* GPIO_OUT value put in GPIO_TSx for the GPIO nb 0 */
-#define GPIO_ALT2_SEL 0x80000000 /* GPIO_OUT value put in GPIO_TSx for the GPIO nb 1 */
-#define GPIO_ALT3_SEL 0xC0000000 /* GPIO_OUT value put in GPIO_TSx for the GPIO nb 2 */
-#define GPIO_MASK 0xC0000000 /* GPIO_MASK */
-#define GPIO_IN_SEL 0x40000000 /* GPIO_IN value put in GPIO_ISx for the GPIO nb 0 */
- /* For the other GPIO number, you must shift */
-
-#ifndef __ASSEMBLY__
-
-typedef enum gpio_select { GPIO_SEL, GPIO_ALT1, GPIO_ALT2, GPIO_ALT3 } gpio_select_t;
-typedef enum gpio_driver { GPIO_DIS, GPIO_IN, GPIO_OUT, GPIO_BI } gpio_driver_t;
-
-typedef struct { unsigned long add; /* gpio core base address */
- gpio_driver_t in_out; /* Driver Setting */
- gpio_select_t alt_nb; /* Selected Alternate */
-} gpio_param_s;
-
-
-#endif /* __ASSEMBLY__ */
-
/*
* Macros for accessing the indirect EBC registers
*/
-#define mtebc(reg, data) mtdcr(ebccfga,reg);mtdcr(ebccfgd,data)
-#define mfebc(reg, data) mtdcr(ebccfga,reg);data = mfdcr(ebccfgd)
+#define mtebc(reg, data) do { mtdcr(ebccfga,reg);mtdcr(ebccfgd,data); } while (0)
+#define mfebc(reg, data) do { mtdcr(ebccfga,reg);data = mfdcr(ebccfgd); } while (0)
/*
* Macros for accessing the indirect SDRAM controller registers
*/
-#define mtsdram(reg, data) mtdcr(memcfga,reg);mtdcr(memcfgd,data)
-#define mfsdram(reg, data) mtdcr(memcfga,reg);data = mfdcr(memcfgd)
+#define mtsdram(reg, data) do { mtdcr(memcfga,reg);mtdcr(memcfgd,data); } while (0)
+#define mfsdram(reg, data) do { mtdcr(memcfga,reg);data = mfdcr(memcfgd); } while (0)
/*
* Macros for accessing the indirect clocking controller registers
*/
-#define mtclk(reg, data) mtdcr(clkcfga,reg);mtdcr(clkcfgd,data)
-#define mfclk(reg, data) mtdcr(clkcfga,reg);data = mfdcr(clkcfgd)
+#define mtclk(reg, data) do { mtdcr(clkcfga,reg);mtdcr(clkcfgd,data); } while (0)
+#define mfclk(reg, data) do { mtdcr(clkcfga,reg);data = mfdcr(clkcfgd); } while (0)
/*
* Macros for accessing the sdr controller registers
*/
-#define mtsdr(reg, data) mtdcr(sdrcfga,reg);mtdcr(sdrcfgd,data)
-#define mfsdr(reg, data) mtdcr(sdrcfga,reg);data = mfdcr(sdrcfgd)
+#define mtsdr(reg, data) do { mtdcr(sdrcfga,reg);mtdcr(sdrcfgd,data); } while (0)
+#define mfsdr(reg, data) do { mtdcr(sdrcfga,reg);data = mfdcr(sdrcfgd); } while (0)
+/*
+ * All 44x except 440GP have CPR registers (indirect DCR)
+ */
+#if !defined(CONFIG_440GP)
+#define CPR0_CFGADDR 0x00C
+#define CPR0_CFGDATA 0x00D
+
+#define mtcpr(reg, data) do { \
+ mtdcr(CPR0_CFGADDR, reg); \
+ mtdcr(CPR0_CFGDATA, data); \
+ } while (0)
+
+#define mfcpr(reg, data) do { \
+ mtdcr(CPR0_CFGADDR, reg); \
+ data = mfdcr(CPR0_CFGDATA); \
+ } while (0)
+#endif
#ifndef __ASSEMBLY__
unsigned long pciClkSync; /* PCI clock is synchronous */
} PPC440_SYS_INFO;
+static inline u32 get_mcsr(void)
+{
+ u32 val;
+
+ asm volatile("mfspr %0, 0x23c" : "=r" (val) :);
+ return val;
+}
+
+static inline void set_mcsr(u32 val)
+{
+ asm volatile("mtspr 0x23c, %0" : "=r" (val) :);
+}
+
#endif /* _ASMLANGUAGE */
#define RESET_VECTOR 0xfffffffc
projects / platform / kernel / u-boot.git / blobdiff