Merge branch 'master' of /home/git/u-boot

[platform/kernel/u-boot.git] / include / ppc405.h

diff --git a/include/ppc405.h b/include/ppc405.h
index e5051d4..cbfe89e 100644 (file)
--- a/include/ppc405.h
+++ b/include/ppc405.h
@@ -784,6 +784,14 @@
 #define reset   (CNTRL_DCR_BASE+0x3)  /* reset register                             */
 #define strap   (CNTRL_DCR_BASE+0x4)  /* strap register                             */
 
+#define CPC0_CR0  (CNTRL_DCR_BASE+0x1)  /* chip control register 0          */
+#define CPC0_CR1  (CNTRL_DCR_BASE+0x2)  /* chip control register 1          */
+#define CPC0_PSR  (CNTRL_DCR_BASE+0x4)  /* chip pin strapping register      */
+
+/* CPC0_ECR/CPC0_EIRR: PPC405GPr only */
+#define CPC0_EIRR (CNTRL_DCR_BASE+0x6) /* external interrupt routing register */
+#define CPC0_ECR  (0xaa)               /* edge conditioner register */
+
 #define ecr     (0xaa)                /* edge conditioner register (405gpr)  */
 
 /* Bit definitions */
@@ -1574,6 +1582,19 @@
 #define   SDR0_CUST0_CHIPSELGAT_EN1   0x00000004       /* Chip Select1 Gating Enable */
 #define   SDR0_CUST0_CHIPSELGAT_EN2   0x00000002       /* Chip Select2 Gating Enable */
 #define   SDR0_CUST0_CHIPSELGAT_EN3   0x00000001       /* Chip Select3 Gating Enable */
+
+#define SDR0_PFC0              0x4100
+#define SDR0_PFC1              0x4101
+#define SDR0_PFC1_U1ME         0x02000000
+#define SDR0_PFC1_U0ME         0x00080000
+#define SDR0_PFC1_U0IM         0x00040000
+#define SDR0_PFC1_SIS          0x00020000
+#define SDR0_PFC1_DMAAEN       0x00010000
+#define SDR0_PFC1_DMADEN       0x00008000
+#define SDR0_PFC1_USBEN                0x00004000
+#define SDR0_PFC1_AHBSWAP      0x00000020
+#define SDR0_PFC1_USBBIGEN     0x00000010
+#define SDR0_PFC1_GPT_FREQ     0x0000000f
 #endif
 
 #endif /* __PPC405_H__ */