/*
* Copyright 2011 Freescale Semiconductor, Inc.
- * Andy Fleming <afleming@freescale.com>
+ * Andy Fleming <afleming@gmail.com>
*
* SPDX-License-Identifier: GPL-2.0+
*
#define PHY_10G_FEATURES (PHY_GBIT_FEATURES | \
SUPPORTED_10000baseT_Full)
+#ifndef PHY_ANEG_TIMEOUT
#define PHY_ANEG_TIMEOUT 4000
+#endif
typedef enum {
PHY_INTERFACE_MODE_MII,
PHY_INTERFACE_MODE_GMII,
PHY_INTERFACE_MODE_SGMII,
+ PHY_INTERFACE_MODE_SGMII_2500,
PHY_INTERFACE_MODE_QSGMII,
PHY_INTERFACE_MODE_TBI,
PHY_INTERFACE_MODE_RMII,
[PHY_INTERFACE_MODE_MII] = "mii",
[PHY_INTERFACE_MODE_GMII] = "gmii",
[PHY_INTERFACE_MODE_SGMII] = "sgmii",
+ [PHY_INTERFACE_MODE_SGMII_2500] = "sgmii-2500",
[PHY_INTERFACE_MODE_QSGMII] = "qsgmii",
[PHY_INTERFACE_MODE_TBI] = "tbi",
[PHY_INTERFACE_MODE_RMII] = "rmii",
/* Called when bringing down the controller */
int (*shutdown)(struct phy_device *phydev);
+ int (*readext)(struct phy_device *phydev, int addr, int devad, int reg);
+ int (*writeext)(struct phy_device *phydev, int addr, int devad, int reg,
+ u16 val);
struct list_head list;
};
u32 flags;
};
+struct fixed_link {
+ int phy_id;
+ int duplex;
+ int link_speed;
+ int pause;
+ int asym_pause;
+};
+
static inline int phy_read(struct phy_device *phydev, int devad, int regnum)
{
struct mii_dev *bus = phydev->bus;
int gen10g_shutdown(struct phy_device *phydev);
int gen10g_discover_mmds(struct phy_device *phydev);
+int phy_aquantia_init(void);
int phy_atheros_init(void);
int phy_broadcom_init(void);
+int phy_cortina_init(void);
int phy_davicom_init(void);
int phy_et1011c_init(void);
int phy_lxt_init(void);
int phy_teranetics_init(void);
int phy_vitesse_init(void);
+int board_phy_config(struct phy_device *phydev);
+
/* PHY UIDs for various PHYs that are referenced in external code */
+#define PHY_UID_CS4340 0x13e51002
#define PHY_UID_TN2020 0x00a19410
#endif