#define PCI_CLASS_PROG 0x09 /* Reg. Level Programming Interface */
#define PCI_CLASS_DEVICE 0x0a /* Device class */
#define PCI_CLASS_CODE 0x0b /* Device class code */
-#define PCI_CLASS_CODE_TOO_OLD 0x00
-#define PCI_CLASS_CODE_STORAGE 0x01
-#define PCI_CLASS_CODE_NETWORK 0x02
-#define PCI_CLASS_CODE_DISPLAY 0x03
-#define PCI_CLASS_CODE_MULTIMEDIA 0x04
-#define PCI_CLASS_CODE_MEMORY 0x05
-#define PCI_CLASS_CODE_BRIDGE 0x06
-#define PCI_CLASS_CODE_COMM 0x07
-#define PCI_CLASS_CODE_PERIPHERAL 0x08
-#define PCI_CLASS_CODE_INPUT 0x09
-#define PCI_CLASS_CODE_DOCKING 0x0A
-#define PCI_CLASS_CODE_PROCESSOR 0x0B
-#define PCI_CLASS_CODE_SERIAL 0x0C
-#define PCI_CLASS_CODE_WIRELESS 0x0D
-#define PCI_CLASS_CODE_I2O 0x0E
-#define PCI_CLASS_CODE_SATELLITE 0x0F
-#define PCI_CLASS_CODE_CRYPTO 0x10
-#define PCI_CLASS_CODE_DATA 0x11
-/* Base Class 0x12 - 0xFE is reserved */
-#define PCI_CLASS_CODE_OTHER 0xFF
-
#define PCI_CLASS_SUB_CODE 0x0a /* Device sub-class code */
-#define PCI_CLASS_SUB_CODE_TOO_OLD_NOTVGA 0x00
-#define PCI_CLASS_SUB_CODE_TOO_OLD_VGA 0x01
-#define PCI_CLASS_SUB_CODE_STORAGE_SCSI 0x00
-#define PCI_CLASS_SUB_CODE_STORAGE_IDE 0x01
-#define PCI_CLASS_SUB_CODE_STORAGE_FLOPPY 0x02
-#define PCI_CLASS_SUB_CODE_STORAGE_IPIBUS 0x03
-#define PCI_CLASS_SUB_CODE_STORAGE_RAID 0x04
-#define PCI_CLASS_SUB_CODE_STORAGE_ATA 0x05
-#define PCI_CLASS_SUB_CODE_STORAGE_SATA 0x06
-#define PCI_CLASS_SUB_CODE_STORAGE_SAS 0x07
-#define PCI_CLASS_SUB_CODE_STORAGE_OTHER 0x80
-#define PCI_CLASS_SUB_CODE_NETWORK_ETHERNET 0x00
-#define PCI_CLASS_SUB_CODE_NETWORK_TOKENRING 0x01
-#define PCI_CLASS_SUB_CODE_NETWORK_FDDI 0x02
-#define PCI_CLASS_SUB_CODE_NETWORK_ATM 0x03
-#define PCI_CLASS_SUB_CODE_NETWORK_ISDN 0x04
-#define PCI_CLASS_SUB_CODE_NETWORK_WORLDFIP 0x05
-#define PCI_CLASS_SUB_CODE_NETWORK_PICMG 0x06
-#define PCI_CLASS_SUB_CODE_NETWORK_OTHER 0x80
-#define PCI_CLASS_SUB_CODE_DISPLAY_VGA 0x00
-#define PCI_CLASS_SUB_CODE_DISPLAY_XGA 0x01
-#define PCI_CLASS_SUB_CODE_DISPLAY_3D 0x02
-#define PCI_CLASS_SUB_CODE_DISPLAY_OTHER 0x80
-#define PCI_CLASS_SUB_CODE_MULTIMEDIA_VIDEO 0x00
-#define PCI_CLASS_SUB_CODE_MULTIMEDIA_AUDIO 0x01
-#define PCI_CLASS_SUB_CODE_MULTIMEDIA_PHONE 0x02
-#define PCI_CLASS_SUB_CODE_MULTIMEDIA_OTHER 0x80
-#define PCI_CLASS_SUB_CODE_MEMORY_RAM 0x00
-#define PCI_CLASS_SUB_CODE_MEMORY_FLASH 0x01
-#define PCI_CLASS_SUB_CODE_MEMORY_OTHER 0x80
-#define PCI_CLASS_SUB_CODE_BRIDGE_HOST 0x00
-#define PCI_CLASS_SUB_CODE_BRIDGE_ISA 0x01
-#define PCI_CLASS_SUB_CODE_BRIDGE_EISA 0x02
-#define PCI_CLASS_SUB_CODE_BRIDGE_MCA 0x03
-#define PCI_CLASS_SUB_CODE_BRIDGE_PCI 0x04
-#define PCI_CLASS_SUB_CODE_BRIDGE_PCMCIA 0x05
-#define PCI_CLASS_SUB_CODE_BRIDGE_NUBUS 0x06
-#define PCI_CLASS_SUB_CODE_BRIDGE_CARDBUS 0x07
-#define PCI_CLASS_SUB_CODE_BRIDGE_RACEWAY 0x08
-#define PCI_CLASS_SUB_CODE_BRIDGE_SEMI_PCI 0x09
-#define PCI_CLASS_SUB_CODE_BRIDGE_INFINIBAND 0x0A
-#define PCI_CLASS_SUB_CODE_BRIDGE_OTHER 0x80
-#define PCI_CLASS_SUB_CODE_COMM_SERIAL 0x00
-#define PCI_CLASS_SUB_CODE_COMM_PARALLEL 0x01
-#define PCI_CLASS_SUB_CODE_COMM_MULTIPORT 0x02
-#define PCI_CLASS_SUB_CODE_COMM_MODEM 0x03
-#define PCI_CLASS_SUB_CODE_COMM_GPIB 0x04
-#define PCI_CLASS_SUB_CODE_COMM_SMARTCARD 0x05
-#define PCI_CLASS_SUB_CODE_COMM_OTHER 0x80
-#define PCI_CLASS_SUB_CODE_PERIPHERAL_PIC 0x00
-#define PCI_CLASS_SUB_CODE_PERIPHERAL_DMA 0x01
-#define PCI_CLASS_SUB_CODE_PERIPHERAL_TIMER 0x02
-#define PCI_CLASS_SUB_CODE_PERIPHERAL_RTC 0x03
-#define PCI_CLASS_SUB_CODE_PERIPHERAL_HOTPLUG 0x04
-#define PCI_CLASS_SUB_CODE_PERIPHERAL_SD 0x05
-#define PCI_CLASS_SUB_CODE_PERIPHERAL_OTHER 0x80
-#define PCI_CLASS_SUB_CODE_INPUT_KEYBOARD 0x00
-#define PCI_CLASS_SUB_CODE_INPUT_DIGITIZER 0x01
-#define PCI_CLASS_SUB_CODE_INPUT_MOUSE 0x02
-#define PCI_CLASS_SUB_CODE_INPUT_SCANNER 0x03
-#define PCI_CLASS_SUB_CODE_INPUT_GAMEPORT 0x04
-#define PCI_CLASS_SUB_CODE_INPUT_OTHER 0x80
-#define PCI_CLASS_SUB_CODE_DOCKING_GENERIC 0x00
-#define PCI_CLASS_SUB_CODE_DOCKING_OTHER 0x80
-#define PCI_CLASS_SUB_CODE_PROCESSOR_386 0x00
-#define PCI_CLASS_SUB_CODE_PROCESSOR_486 0x01
-#define PCI_CLASS_SUB_CODE_PROCESSOR_PENTIUM 0x02
-#define PCI_CLASS_SUB_CODE_PROCESSOR_ALPHA 0x10
-#define PCI_CLASS_SUB_CODE_PROCESSOR_POWERPC 0x20
-#define PCI_CLASS_SUB_CODE_PROCESSOR_MIPS 0x30
-#define PCI_CLASS_SUB_CODE_PROCESSOR_COPROC 0x40
-#define PCI_CLASS_SUB_CODE_SERIAL_1394 0x00
-#define PCI_CLASS_SUB_CODE_SERIAL_ACCESSBUS 0x01
-#define PCI_CLASS_SUB_CODE_SERIAL_SSA 0x02
-#define PCI_CLASS_SUB_CODE_SERIAL_USB 0x03
-#define PCI_CLASS_SUB_CODE_SERIAL_FIBRECHAN 0x04
-#define PCI_CLASS_SUB_CODE_SERIAL_SMBUS 0x05
-#define PCI_CLASS_SUB_CODE_SERIAL_INFINIBAND 0x06
-#define PCI_CLASS_SUB_CODE_SERIAL_IPMI 0x07
-#define PCI_CLASS_SUB_CODE_SERIAL_SERCOS 0x08
-#define PCI_CLASS_SUB_CODE_SERIAL_CANBUS 0x09
-#define PCI_CLASS_SUB_CODE_WIRELESS_IRDA 0x00
-#define PCI_CLASS_SUB_CODE_WIRELESS_IR 0x01
-#define PCI_CLASS_SUB_CODE_WIRELESS_RF 0x10
-#define PCI_CLASS_SUB_CODE_WIRELESS_BLUETOOTH 0x11
-#define PCI_CLASS_SUB_CODE_WIRELESS_BROADBAND 0x12
-#define PCI_CLASS_SUB_CODE_WIRELESS_80211A 0x20
-#define PCI_CLASS_SUB_CODE_WIRELESS_80211B 0x21
-#define PCI_CLASS_SUB_CODE_WIRELESS_OTHER 0x80
-#define PCI_CLASS_SUB_CODE_I2O_V1_0 0x00
-#define PCI_CLASS_SUB_CODE_SATELLITE_TV 0x01
-#define PCI_CLASS_SUB_CODE_SATELLITE_AUDIO 0x02
-#define PCI_CLASS_SUB_CODE_SATELLITE_VOICE 0x03
-#define PCI_CLASS_SUB_CODE_SATELLITE_DATA 0x04
-#define PCI_CLASS_SUB_CODE_CRYPTO_NETWORK 0x00
-#define PCI_CLASS_SUB_CODE_CRYPTO_ENTERTAINMENT 0x10
-#define PCI_CLASS_SUB_CODE_CRYPTO_OTHER 0x80
-#define PCI_CLASS_SUB_CODE_DATA_DPIO 0x00
-#define PCI_CLASS_SUB_CODE_DATA_PERFCNTR 0x01
-#define PCI_CLASS_SUB_CODE_DATA_COMMSYNC 0x10
-#define PCI_CLASS_SUB_CODE_DATA_MGMT 0x20
-#define PCI_CLASS_SUB_CODE_DATA_OTHER 0x80
#define PCI_CACHE_LINE_SIZE 0x0c /* 8 bits */
#define PCI_LATENCY_TIMER 0x0d /* 8 bits */
#define PCI_EXP_DEVCAP 4 /* Device capabilities */
#define PCI_EXP_DEVCAP_FLR 0x10000000 /* Function Level Reset */
#define PCI_EXP_DEVCTL 8 /* Device Control */
+#define PCI_EXP_DEVCTL_PAYLOAD 0x00e0 /* Max_Payload_Size */
+#define PCI_EXP_DEVCTL_PAYLOAD_128B 0x0000 /* 128 Bytes */
+#define PCI_EXP_DEVCTL_PAYLOAD_256B 0x0020 /* 256 Bytes */
+#define PCI_EXP_DEVCTL_PAYLOAD_512B 0x0040 /* 512 Bytes */
+#define PCI_EXP_DEVCTL_PAYLOAD_1024B 0x0060 /* 1024 Bytes */
+#define PCI_EXP_DEVCTL_PAYLOAD_2048B 0x0080 /* 2048 Bytes */
+#define PCI_EXP_DEVCTL_PAYLOAD_4096B 0x00a0 /* 4096 Bytes */
+#define PCI_EXP_DEVCTL_RELAX_EN 0x0010 /* Enable relaxed ordering */
+#define PCI_EXP_DEVCTL_NOSNOOP_EN 0x0800 /* Enable No Snoop */
+#define PCI_EXP_DEVCTL_READRQ 0x7000 /* Max_Read_Request_Size */
+#define PCI_EXP_DEVCTL_READRQ_128B 0x0000 /* 128 Bytes */
+#define PCI_EXP_DEVCTL_READRQ_256B 0x1000 /* 256 Bytes */
+#define PCI_EXP_DEVCTL_READRQ_512B 0x2000 /* 512 Bytes */
+#define PCI_EXP_DEVCTL_READRQ_1024B 0x3000 /* 1024 Bytes */
+#define PCI_EXP_DEVCTL_READRQ_2048B 0x4000 /* 2048 Bytes */
+#define PCI_EXP_DEVCTL_READRQ_4096B 0x5000 /* 4096 Bytes */
#define PCI_EXP_DEVCTL_BCR_FLR 0x8000 /* Bridge Configuration Retry / FLR */
#define PCI_EXP_LNKCAP 12 /* Link Capabilities */
#define PCI_EXP_LNKCAP_SLS 0x0000000f /* Supported Link Speeds */
#define PCI_EXP_LNKCTL2_TLS_5_0GT 0x0002 /* Target Link Speed 5.0GT/s */
#define PCI_EXP_LNKCTL2_TLS_8_0GT 0x0003 /* Target Link Speed 8.0GT/s */
+/* Advanced Error Reporting */
+#define PCI_ERR_CAP 24 /* Advanced Error Capabilities */
+#define PCI_ERR_CAP_FEP(x) ((x) & 31) /* First Error Pointer */
+#define PCI_ERR_CAP_ECRC_GENC 0x00000020 /* ECRC Generation Capable */
+#define PCI_ERR_CAP_ECRC_GENE 0x00000040 /* ECRC Generation Enable */
+#define PCI_ERR_CAP_ECRC_CHKC 0x00000080 /* ECRC Check Capable */
+#define PCI_ERR_CAP_ECRC_CHKE 0x00000100 /* ECRC Check Enable */
+
/* Single Root I/O Virtualization Registers */
#define PCI_SRIOV_CAP 0x04 /* SR-IOV Capabilities */
#define PCI_SRIOV_CTRL 0x08 /* SR-IOV Control */
* @size: Amount of bytes to allocate
* @bar: Returns the PCI bus address of the allocated resource
* @supports_64bit: Whether to allow allocations above the 32-bit boundary
- * @return 0 if successful, -1 on failure
+ * Return: 0 if successful, -1 on failure
*/
int pciauto_region_allocate(struct pci_region *res, pci_size_t size,
pci_addr_t *bar, bool supports_64bit);
* @hose: PCI hose to use
* @dev: PCI device to inspect
* @barnum: BAR number (0-5)
- * @return address of the bar, masking out any control bits
+ * Return: address of the bar, masking out any control bits
* */
u32 pci_read_bar32(struct pci_controller *hose, pci_dev_t dev, int barnum);
* dm_pci_get_bdf() - Get the BDF value for a device
*
* @dev: Device to check
- * @return bus/device/function value (see PCI_BDF())
+ * Return: bus/device/function value (see PCI_BDF())
*/
pci_dev_t dm_pci_get_bdf(const struct udevice *dev);
* driver interface.
*
* @bus: Bus containing devices to bind
- * @return 0 if OK, -ve on error
+ * Return: 0 if OK, -ve on error
*/
int pci_bind_bus_devices(struct udevice *bus);
* devices are mapped into memory and I/O space ready for use.
*
* @bus: Bus containing devices to bind
- * @return 0 if OK, -ve on error
+ * Return: 0 if OK, -ve on error
*/
int pci_auto_config_devices(struct udevice *bus);
*
* @bdf: PCI device address: bus, device and function -see PCI_BDF()
* @devp: Returns the device for this address, if found
- * @return 0 if OK, -ENODEV if not found
+ * Return: 0 if OK, -ENODEV if not found
*/
int dm_pci_bus_find_bdf(pci_dev_t bdf, struct udevice **devp);
*
* @find_devfn: PCI device address (device and function only)
* @devp: Returns the device for this address, if found
- * @return 0 if OK, -ENODEV if not found
+ * Return: 0 if OK, -ENODEV if not found
*/
int pci_bus_find_devfn(const struct udevice *bus, pci_dev_t find_devfn,
struct udevice **devp);
*
* @devp: Set to the first available device, or NULL if no more are left
* or we got an error
- * @return 0 if all is OK, -ve on error (e.g. a bus/bridge failed to probe)
+ * Return: 0 if all is OK, -ve on error (e.g. a bus/bridge failed to probe)
*/
int pci_find_first_device(struct udevice **devp);
*
* @devp: On entry, the last device returned. Set to the next available
* device, or NULL if no more are left or we got an error
- * @return 0 if all is OK, -ve on error (e.g. a bus/bridge failed to probe)
+ * Return: 0 if all is OK, -ve on error (e.g. a bus/bridge failed to probe)
*/
int pci_find_next_device(struct udevice **devp);
* pci_get_ff() - Returns a mask for the given access size
*
* @size: Access size
- * @return 0xff for PCI_SIZE_8, 0xffff for PCI_SIZE_16, 0xffffffff for
+ * Return: 0xff for PCI_SIZE_8, 0xffff for PCI_SIZE_16, 0xffffffff for
* PCI_SIZE_32
*/
int pci_get_ff(enum pci_size_t size);
* parameter is decremented for each non-matching device so
* can be called repeatedly.
* @devp: Returns matching device if found
- * @return 0 if found, -ENODEV if not
+ * Return: 0 if found, -ENODEV if not
*/
int pci_bus_find_devices(struct udevice *bus, const struct pci_device_id *ids,
int *indexp, struct udevice **devp);
* @index: Index number of device to find, 0 for the first match, 1 for
* the second, etc.
* @devp: Returns matching device if found
- * @return 0 if found, -ENODEV if not
+ * Return: 0 if found, -ENODEV if not
*/
int pci_find_device_id(const struct pci_device_id *ids, int index,
struct udevice **devp);
*
* @hose: PCI hose to scan
* @bdf: PCI bus address to scan (PCI_BUS(bdf) is the bus number)
- * @return 0 if OK, -ve on error
+ * Return: 0 if OK, -ve on error
*/
int dm_pci_hose_probe_bus(struct udevice *bus);
* @offset: Register offset to read
* @valuep: Place to put the returned value
* @size: Access size
- * @return 0 if OK, -ve on error
+ * Return: 0 if OK, -ve on error
*/
int pci_bus_read_config(const struct udevice *bus, pci_dev_t bdf, int offset,
unsigned long *valuep, enum pci_size_t size);
* @offset: Register offset to write
* @value: Value to write
* @size: Access size
- * @return 0 if OK, -ve on error
+ * Return: 0 if OK, -ve on error
*/
int pci_bus_write_config(struct udevice *bus, pci_dev_t bdf, int offset,
unsigned long value, enum pci_size_t size);
* @offset: Register offset to update
* @clr: Bits to clear
* @set: Bits to set
- * @return 0 if OK, -ve on error
+ * Return: 0 if OK, -ve on error
*/
int pci_bus_clrset_config32(struct udevice *bus, pci_dev_t bdf, int offset,
u32 clr, u32 set);
*
* @pdev: Physical Function udevice handle
* @vf_en: Number of Virtual Function devices to enable
- * @return 0 on success, -ve on error
+ * Return: 0 on success, -ve on error
*/
int pci_sriov_init(struct udevice *pdev, int vf_en);
* pci_sriov_get_totalvfs() - Get total available Virtual Function devices
*
* @pdev: Physical Function udevice handle
- * @return count on success, -ve on error
+ * Return: count on success, -ve on error
*/
int pci_sriov_get_totalvfs(struct udevice *pdev);
#endif
* devices are mapped into memory and I/O space ready for use.
*
* @dev: Device to configure
- * @return 0 if OK, -ve on error
+ * Return: 0 if OK, -ve on error
*/
int dm_pciauto_config_device(struct udevice *dev);
* @value: Value to transform (32-bit value read from @offset & ~3)
* @offset: Register offset that was read
* @size: Required size of the result
- * @return the value that would have been obtained if the read had been
+ * Return: the value that would have been obtained if the read had been
* performed at the given offset with the correct size
*/
ulong pci_conv_32_to_size(ulong value, uint offset, enum pci_size_t size);
* @value: Value to transform (32-bit value read from @offset & ~3)
* @offset: Register offset that should be written
* @size: Required size of the write
- * @return the value that should be written as a 32-bit access to @offset & ~3.
+ * Return: the value that should be written as a 32-bit access to @offset & ~3.
*/
ulong pci_conv_size_to_32(ulong old, ulong value, uint offset,
enum pci_size_t size);
* pci_get_controller() - obtain the controller to use for a bus
*
* @dev: Device to check
- * @return pointer to the controller device for this bus
+ * Return: pointer to the controller device for this bus
*/
struct udevice *pci_get_controller(struct udevice *dev);
* @iop: Returns a pointer to the I/O region, or NULL if none
* @memp: Returns a pointer to the memory region, or NULL if none
* @prefp: Returns a pointer to the pre-fetch region, or NULL if none
- * @return the number of non-NULL regions returned, normally 3
+ * Return: the number of non-NULL regions returned, normally 3
*/
int pci_get_regions(struct udevice *dev, struct pci_region **iop,
struct pci_region **memp, struct pci_region **prefp);
* @dev: Device containing the PCI address
* @addr: PCI address to convert
* @flags: Flags for the region type (PCI_REGION_...)
- * @return physical address corresponding to that PCI bus address
+ * Return: physical address corresponding to that PCI bus address
*/
phys_addr_t dm_pci_bus_to_phys(struct udevice *dev, pci_addr_t addr,
unsigned long flags);
* @dev: Device containing the bus address
* @addr: Physical address to convert
* @flags: Flags for the region type (PCI_REGION_...)
- * @return PCI bus address corresponding to that physical address
+ * Return: PCI bus address corresponding to that physical address
*/
pci_addr_t dm_pci_phys_to_bus(struct udevice *dev, phys_addr_t addr,
unsigned long flags);
* @device: Device ID
* @index: 0 to find the first match, 1 for second, etc.
* @devp: Returns pointer to the device, if found
- * @return 0 if found, -ve on error
+ * Return: 0 if found, -ve on error
*/
int dm_pci_find_device(unsigned int vendor, unsigned int device, int index,
struct udevice **devp);
* @find_class: 3-byte (24-bit) class value to find
* @index: 0 to find the first match, 1 for second, etc.
* @devp: Returns pointer to the device, if found
- * @return 0 if found, -ve on error
+ * Return: 0 if found, -ve on error
*/
int dm_pci_find_class(uint find_class, int index, struct udevice **devp);
* @find_devfn: PCI device and function address (PCI_DEVFN())
* @containerp: Returns container device if found
* @emulp: Returns emulated device if found
- * @return 0 if found, -ENODEV if not found
+ * Return: 0 if found, -ENODEV if not found
*/
int sandbox_pci_get_emul(const struct udevice *bus, pci_dev_t find_devfn,
struct udevice **containerp, struct udevice **emulp);
*
* @emul: Emulation device to check
* @devp: Returns the client device emulated by this device
- * @return 0 if OK, -ENOENT if the device has no client yet
+ * Return: 0 if OK, -ENOENT if the device has no client yet
*/
int sandbox_pci_get_client(struct udevice *emul, struct udevice **devp);
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