#define PCI_BRIDGE_CTL_BUS_RESET 0x40 /* Secondary bus reset */
#define PCI_BRIDGE_CTL_FAST_BACK 0x80 /* Fast Back2Back enabled on secondary interface */
+/* From 440ep */
+#define PCI_ERREN 0x48 /* Error Enable */
+#define PCI_ERRSTS 0x49 /* Error Status */
+#define PCI_BRDGOPT1 0x4A /* PCI Bridge Options 1 */
+#define PCI_PLBSESR0 0x4C /* PCI PLB Slave Error Syndrome 0 */
+#define PCI_PLBSESR1 0x50 /* PCI PLB Slave Error Syndrome 1 */
+#define PCI_PLBSEAR 0x54 /* PCI PLB Slave Error Address */
+#define PCI_CAPID 0x58 /* Capability Identifier */
+#define PCI_NEXTITEMPTR 0x59 /* Next Item Pointer */
+#define PCI_PMC 0x5A /* Power Management Capabilities */
+#define PCI_PMCSR 0x5C /* Power Management Control Status */
+#define PCI_PMCSRBSE 0x5E /* PMCSR PCI to PCI Bridge Support Extensions */
+#define PCI_BRDGOPT2 0x60 /* PCI Bridge Options 2 */
+#define PCI_PMSCRR 0x64 /* Power Management State Change Request Re. */
+
/* Header type 2 (CardBus bridges) */
#define PCI_CB_CAPABILITY_LIST 0x14
/* 0x15 reserved */
#define PCI_AGP_COMMAND_RATE1 0x0001 /* Use 4x rate */
#define PCI_AGP_SIZEOF 12
+/* PCI-X registers */
+
+#define PCI_X_CMD_DPERR_E 0x0001 /* Data Parity Error Recovery Enable */
+#define PCI_X_CMD_ERO 0x0002 /* Enable Relaxed Ordering */
+#define PCI_X_CMD_MAX_READ 0x0000 /* Max Memory Read Byte Count */
+#define PCI_X_CMD_MAX_SPLIT 0x0030 /* Max Outstanding Split Transactions */
+#define PCI_X_CMD_VERSION(x) (((x) >> 12) & 3) /* Version */
+
+
/* Slot Identification */
#define PCI_SID_ESR 2 /* Expansion Slot Register */
#define PCI_MAX_PCI_DEVICES 32
#define PCI_MAX_PCI_FUNCTIONS 8
+#define PCI_DCR 0x54 /* PCIe Device Control Register */
+#define PCI_DSR 0x56 /* PCIe Device Status Register */
+#define PCI_LSR 0x5e /* PCIe Link Status Register */
+#define PCI_LTSSM 0x404 /* PCIe Link Training, Status State Machine */
+#define PCI_LTSSM_L0 0x16 /* L0 state */
+
/* Include the ID list */
#include <pci_ids.h>
struct pci_region {
unsigned long bus_start; /* Start on the bus */
- unsigned long phys_start; /* Start in physical address space */
+ phys_addr_t phys_start; /* Start in physical address space */
unsigned long size; /* Size */
unsigned long flags; /* Resource flags */
#define PCI_REGION_MEM 0x00000000 /* PCI memory space */
#define PCI_REGION_IO 0x00000001 /* PCI IO space */
#define PCI_REGION_TYPE 0x00000001
+#define PCI_REGION_PREFETCH 0x00000008 /* prefetchable PCI memory */
#define PCI_REGION_MEMORY 0x00000100 /* System memory */
#define PCI_REGION_RO 0x00000200 /* Read-only memory */
extern __inline__ void pci_set_region(struct pci_region *reg,
unsigned long bus_start,
- unsigned long phys_start,
+ phys_addr_t phys_start,
unsigned long size,
unsigned long flags) {
reg->bus_start = bus_start;
unsigned long priv[3];
};
-extern void pci_cfgfunc_nothing(struct pci_controller* hose, pci_dev_t dev,
- struct pci_config_table *);
+extern void pci_cfgfunc_do_nothing(struct pci_controller* hose, pci_dev_t dev,
+ struct pci_config_table *);
extern void pci_cfgfunc_config_device(struct pci_controller* hose, pci_dev_t dev,
struct pci_config_table *);
int (*write_dword)(struct pci_controller*, pci_dev_t, int where, u32);
/* Used by auto config */
- struct pci_region *pci_mem, *pci_io;
+ struct pci_region *pci_mem, *pci_io, *pci_prefetch;
/* Used by ppc405 autoconfig*/
struct pci_region *pci_fb;
extern void pci_setup_indirect(struct pci_controller* hose, u32 cfg_addr, u32 cfg_data);
-extern unsigned long pci_hose_bus_to_phys(struct pci_controller* hose,
- unsigned long addr, unsigned long flags);
+extern phys_addr_t pci_hose_bus_to_phys(struct pci_controller* hose,
+ unsigned long addr, unsigned long flags);
extern unsigned long pci_hose_phys_to_bus(struct pci_controller* hose,
- unsigned long addr, unsigned long flags);
+ phys_addr_t addr, unsigned long flags);
#define pci_phys_to_bus(dev, addr, flags) \
pci_hose_phys_to_bus(pci_bus_to_hose(PCI_BUS(dev)), (addr), (flags))
extern void pciauto_setup_device(struct pci_controller *hose,
pci_dev_t dev, int bars_num,
struct pci_region *mem,
+ struct pci_region *prefetch,
struct pci_region *io);
int pciauto_config_device(struct pci_controller *hose, pci_dev_t dev);
extern void pci_mpc824x_init (struct pci_controller *hose);
#endif
+#ifdef CONFIG_MPC85xx
+extern void pci_mpc85xx_init (struct pci_controller *hose);
+#endif
#endif /* _PCI_H */