+start-sanitize-am33
+Fri Jun 19 09:39:47 1998 Jeffrey A Law (law@cygnus.com)
+
+ * mn10300.h (MN10300_OPERAND_XRREG): Define.
+ (MN10300_OPERAND_PLUS): Likewise.
+ (FMT_D6, FMT_D7): Likewise.
+
+end-sanitize-am33
+1998-06-18 Ulrich Drepper <drepper@cygnus.com>
+
+ * i386.h: Add support for fxsave, fxrstor, sysenter and sysexit.
+
+start-sanitize-am33
+Wed Jun 17 17:54:08 1998 Jeffrey A Law (law@cygnus.com)
+
+ * mn10300.h (MN10300_OPERAND_USP): Define.
+ (MN10300_OPERAND_SSP, MN10300_OPERAND_MSP): Likewise.
+ (MN10300_OPERAND_PC, MN10300_OPERAND_EPSW): Likewise.
+ (MN10300_OPERAND_RREG): Likewise.
+
+end-sanitize-am33
+Sat Jun 13 11:31:35 1998 Alan Modra <alan@spri.levels.unisa.edu.au>
+
+ * i386.h (i386_optab): Add general form of aad and aam. Add ud2a
+ and ud2b.
+ (i386_regtab): Allow cr0..7, db0..7, dr0..7, tr0..7, not just
+ those that happen to be implemented on pentiums.
+
+Tue Jun 9 12:16:01 1998 Alan Modra <alan@spri.levels.unisa.edu.au>
+
+ * i386.h: Change occurences of Data16 to Size16, Data32 to Size32,
+ IgnoreDataSize to IgnoreSize. Flag address and data size prefixes
+ with Size16|IgnoreSize or Size32|IgnoreSize.
+
+Mon Jun 8 12:15:52 1998 Alan Modra <alan@spri.levels.unisa.edu.au>
+
+ * i386.h (REPNE): Rename to REPNE_PREFIX_OPCODE.
+ (REPE): Rename to REPE_PREFIX_OPCODE.
+ (i386_regtab_end): Remove.
+ (i386_prefixtab, i386_prefixtab_end): Remove.
+ (i386_optab): Use NULL as sentinel rather than "" to suit rewrite
+ of md_begin.
+ (MAX_OPCODE_SIZE): Define.
+ (i386_optab_end): Remove.
+ (sl_Suf): Define.
+ (sl_FP): Use sl_Suf.
+
+ * i386.h (i386_optab): Allow 16 bit displacement for `mov
+ mem,acc'. Combine 16 and 32 bit forms of various insns. Allow 16
+ bit form of ljmp. Add IsPrefix modifier to prefixes. Add addr32,
+ data32, dword, and adword prefixes.
+ (i386_regtab): Add BaseIndex modifier to valid 16 bit base/index
+ regs.
+
+Fri Jun 5 23:42:43 1998 Alan Modra <alan@spri.levels.unisa.edu.au>
+
+ * i386.h (i386_regtab): Remove BaseIndex modifier from esp.
+
+ * i386.h: Allow `l' suffix on fld, fst, fstp, fcom, fcomp with
+ register operands, because this is a common idiom. Flag them with
+ a warning. Allow illegal faddp, fsubp, fsubrp, fmulp, fdivp,
+ fdivrp because gcc erroneously generates them. Also flag with a
+ warning.
+
+ * i386.h: Add suffix modifiers to most insns, and tighter operand
+ checks in some cases. Fix a number of UnixWare compatibility
+ issues with float insns. Merge some floating point opcodes, using
+ new FloatMF modifier.
+ (WORD_PREFIX_OPCODE): Rename to DATA_PREFIX_OPCODE for
+ consistency.
+
+ * i386.h: Change occurence of ShortformW to W|ShortForm. Add
+ IgnoreDataSize where appropriate.
+
+Wed Jun 3 18:28:45 1998 Alan Modra <alan@spri.levels.unisa.edu.au>
+
+ * i386.h: (one_byte_segment_defaults): Remove.
+ (two_byte_segment_defaults): Remove.
+ (i386_regtab): Add BaseIndex to 32 bit regs reg_type.
+
+Fri May 15 15:59:04 1998 Doug Evans <devans@seba.cygnus.com>
+
+ * cgen.h (cgen_hw_lookup_by_name): Renamed from cgen_hw_lookup.
+ (cgen_hw_lookup_by_num): Declare.
+
+Thu May 7 09:27:58 1998 Frank Ch. Eigler <fche@cygnus.com>
+
+ * mips.h (OP_{SH,MASK}_CODE2): Added "q" operand format for lower
+ ten bits of MIPS ISA1 "break" instruction, and for "sdbbp"
+
+Thu May 7 02:14:08 1998 Doug Evans <devans@charmed.cygnus.com>
+
+ * cgen.h (cgen_asm_init_parse): Delete.
+ (cgen_save_fixups,cgen_restore_fixups,cgen_swap_fixups): Delete.
+ (cgen_asm_record_register,cgen_asm_finish_insn): Delete.
+
+Mon Apr 27 10:13:11 1998 Doug Evans <devans@seba.cygnus.com>
+
+ * cgen.h (CGEN_ATTR_TYPE): Delete `const', moved to uses.
+ (cgen_asm_finish_insn): Update prototype.
+ (cgen_insn): New members num, data.
+ (CGEN_INSN_TABLE): Members asm_hash, asm_hash_table_size,
+ dis_hash, dis_hash_table_size moved to ...
+ (CGEN_OPCODE_TABLE). Here. Renamed from CGEN_OPCODE_DATA.
+ All uses updated. New members asm_hash_p, dis_hash_p.
+ (CGEN_MINSN_EXPANSION): New struct.
+ (cgen_expand_macro_insn): Declare.
+ (cgen_macro_insn_count): Declare.
+ (get_insn_operands): Update prototype.
+ (lookup_get_insn_operands): Declare.
+
+Tue Apr 21 17:11:32 1998 Alan Modra <alan@spri.levels.unisa.edu.au>
+
+ * i386.h (i386_optab): Change iclrKludge and imulKludge to
+ regKludge. Add operands types for string instructions.
+
+Mon Apr 20 14:40:29 1998 Tom Tromey <tromey@cygnus.com>
+
+ * i386.h (X): Renamed from `Z_' to preserve formatting of opcode
+ table.
+
Sun Apr 19 13:54:06 1998 Tom Tromey <tromey@cygnus.com>
* i386.h (Z_): Renamed from `_' to avoid clash with common alias
* dvp.h (dvp_expand_macro): Declare.
(vif_macros,vif_macro_count): Declare.
-start-sanitize-sky
+end-sanitize-sky
Fri Apr 3 12:04:48 1998 Alan Modra <alan@spri.levels.unisa.edu.au>
* i386.h: Remove NoModrm flag from all insns: it's never checked.
Wed Jan 14 17:21:43 1998 Nick Clifton <nickc@cygnus.com>
- * cgen.h: Formatting changes to improve readability.
+ * cgen.h: Formatting changes to improve readability.
Mon Jan 12 11:37:36 1998 Doug Evans <devans@seba.cygnus.com>
start-sanitize-tx49
Wed Oct 29 17:33:37 1997 Gavin Koch <gavin@cygnus.com>
- * mips.h (INSN_4900): Added.
+ * mips.h (INSN_4900): Added.
end-sanitize-tx49
Fri Oct 24 22:36:20 1997 Ken Raeburn <raeburn@cygnus.com>
Merge changes from Martin Hunt:
- * d30v.h: Allow up to 64 control registers. Add
+ * d30v.h: Allow up to 64 control registers. Add
SHORT_A5S format.
* d30v.h (LONG_Db): New form for delayed branches.
* d30v.h (SHORT_D2B): New form.
- * d30v.h (SHORT_A2): New form.
+ * d30v.h (SHORT_A2): New form.
- * d30v.h (OPERAND_2REG): Add new operand to indicate 2
+ * d30v.h (OPERAND_2REG): Add new operand to indicate 2
registers are used. Needed for VLIW optimization.
end-sanitize-d30v
Tue Sep 2 15:32:32 1997 Nick Clifton <nickc@cygnus.com>
- * v850.h (V850_OPREAND_ADJUST_SHORT_MEMORY): Removed.
+ * v850.h (V850_OPREAND_ADJUST_SHORT_MEMORY): Removed.
Tue Aug 26 12:21:52 1997 Ian Lance Taylor <ian@cygnus.com>
Mon Aug 18 11:05:58 1997 Nick Clifton <nickc@cygnus.com>
- * v850.h (struct v850_opcode): Remove flags field.
+ * v850.h (struct v850_opcode): Remove flags field.
Wed Aug 13 18:45:48 1997 Nick Clifton <nickc@cygnus.com>
* v850.h (struct v850_opcode): Add flags field.
(struct v850_operand): Extend meaning of 'bits' and 'shift'
- fields.
+ fields.
start-sanitize-v850e
(V850E_INSTRUCTION, V850EA_INSTRUCTION): New flags.
Mon Feb 24 15:15:56 1997 Martin M. Hunt <hunt@pizza.cygnus.com>
- * d10v.h: Change pre_defined_registers to
+ * d10v.h: Change pre_defined_registers to
d10v_predefined_registers and reg_name_cnt to d10v_reg_name_cnt.
Sat Feb 22 21:25:00 1997 Dawn Perchik <dawn@cygnus.com>
* mips.h: Add macros for cop0, cop1 cop2 and cop3.
- Change mips_opcodes from const array to a pointer,
+ Change mips_opcodes from const array to a pointer,
and change bfd_mips_num_opcodes from const int to int,
- so that we can increase the size of the mips opcodes table
+ so that we can increase the size of the mips opcodes table
dynamically.
-
+
start-sanitize-d30v
Fri Feb 21 16:34:18 1997 Martin M. Hunt <hunt@pizza.cygnus.com>
end-sanitize-tic80
start-sanitize-r5900
Fri Feb 7 11:12:44 1997 Gavin Koch <gavin@cygnus.com>
-
+
* mips.h: add r5900.
-
+
end-sanitize-r5900
start-sanitize-tic80
Mon Feb 10 10:32:17 1997 Fred Fish <fnf@cygnus.com>
(TIC80_VECTOR): Define a flag bit for the flags. This one means
that the opcode can have two vector instructions in a single
32 bit word and we have to encode/decode both.
-
+
Tue Jan 14 19:37:09 1997 Fred Fish <fnf@cygnus.com>
* tic80.h (TIC80_OPERAND_PCREL): Renamed from
* mn10200.h: Fix comment, mn10200_operand not powerpc_operand.
* mn10300.h: Fix comment, mn10300_operand not powerpc_operand.
* v850.h: Fix comment, v850_operand not powerpc_operand.
-
+
Mon Dec 9 16:45:39 1996 Jeffrey A Law (law@cygnus.com)
* mn10200.h: Flesh out structures and definitions needed by
Wed Jul 17 14:46:38 1996 Martin M. Hunt <hunt@pizza.cygnus.com>
- * d10v.h: New file.
+ * d10v.h: New file.
Thu Jul 11 12:09:15 1996 Jeffrey A Law (law@cygnus.com)
(EBITOP): Likewise.
(O_LAST): Bump.
(ldc, stc, movb, movw, movl): Use 32bit offsets and absolutes.
-
+
* h8300.h (EXR, SHIFT_2, MACREG, SHIFT_IMM, RDINC): Define.
(O_TAS, O_CLRMAC, O_LDMAC, O_MAC, O_LDM, O_STM): Define.
(BITOP, EBITOP): Handle new H8/S addressing modes for
(UNOP3): Handle new shift/rotate insns on the H8/S.
(insns using exr): New instructions.
(tas, mac, ldmac, clrmac, ldm, stm): New instructions.
-
+
Thu May 23 16:56:48 1996 Jeffrey A Law (law@cygnus.com)
* h8300.h (add.l): Undo Apr 5th change. The manual I had
Thu Jul 7 12:34:48 1994 Steve Chamberlain (sac@jonny.cygnus.com)
- * h8300.h (xor.l) :fix bit pattern.
+ * h8300.h (xor.l) :fix bit pattern.
(L_2): New size of operand.
(trapa): Use it.
Wed Dec 1 12:15:32 1993 Jeffrey A. Law (law@snake.cs.utah.edu)
- * From Hisashi MINAMINO <minamino@sramhc.sra.co.jp>
+ * From Hisashi MINAMINO <minamino@sramhc.sra.co.jp>
* hppa.h: #undef NONE to avoid conflict with hiux include files.
Sun Nov 21 22:06:57 1993 Jeffrey A. Law (law@snake.cs.utah.edu)
Patches from Jeff Law, law@cs.utah.edu:
* hppa.h: Clean up some of the OLD_TABLE, non-OLD_TABLE braindamage.
Make the tables be the same for the following instructions:
- "bb", "addb[tf]", "addib[tf]", "add", "add[loc]", "addco",
+ "bb", "addb[tf]", "addib[tf]", "add", "add[loc]", "addco",
"sh[123]add", "sh[123]add[lo]", "sub", "sub[obt]", "sub[bt]o",
- "ds", "comclr", "addi", "addi[ot]", "addito", "subi", "subio",
- "comiclr", "fadd", "fsub", "fmpy", "fdiv", "fsqrt", "fabs",
- "frnd", "fcpy", "fcnvff", "fcnvxf", "fcnvfx", "fcnvfxt",
+ "ds", "comclr", "addi", "addi[ot]", "addito", "subi", "subio",
+ "comiclr", "fadd", "fsub", "fmpy", "fdiv", "fsqrt", "fabs",
+ "frnd", "fcpy", "fcnvff", "fcnvxf", "fcnvfx", "fcnvfxt",
"fcmp", and "ftest".
* hppa.h: Make new and old tables the same for "break", "mtctl",
Thu Jun 3 15:42:59 1993 Stu Grossman (grossman@cygnus.com)
* Patches from Jeffrey Law <law@cs.utah.edu>.
- * hppa.h: Rework single precision FP
+ * hppa.h: Rework single precision FP
instructions so that they correctly disassemble code
PA1.1 code.
* m68k.h (BREAK_UP_BIG_DECL, AND_OTHER_PART): Add kludge which
allows callers to break up the large initialized struct full of
- opcodes into two half-sized ones. This permits GCC to compile
+ opcodes into two half-sized ones. This permits GCC to compile
this module, since it takes exponential space for initializers.
(numopcodes, endop): Revise to use AND_OTHER_PART in size calcs.
Sat Nov 30 20:40:51 1991 Steve Chamberlain (sac at rtl.cygnus.com)
- * a29k.h, arm.h, h8300.h, i386.h, i860.h, i960.h , m68k.h,
+ * a29k.h, arm.h, h8300.h, i386.h, i860.h, i960.h , m68k.h,
m88k.h, mips.h , np1.h, ns32k.h, pn.h, pyr.h, sparc.h, tahoe.h,
vax.h, ChangeLog: renamed from ../<foo>-opcode.h
projects / platform / upstream / binutils.git / blobdiff