/*
- * Copyright 2004 Freescale Semiconductor.
- * Jeffrey Brown (jeffrey@freescale.com)
+ * Copyright 2006 Freescale Semiconductor.
+ * Jeffrey Brown
* Srikanth Srinivasan (srikanth.srinivasan@freescale.com)
*/
#define __MPC86xx_H__
#define EXC_OFF_SYS_RESET 0x0100 /* System reset offset */
+#define _START_OFFSET EXC_OFF_SYS_RESET
-/*----------------------------------------------------------------
+/*
+ * platform register addresses
+ */
+
+#define GUTS_SVR (CFG_CCSRBAR + 0xE00A4)
+#define MCM_ABCR (CFG_CCSRBAR + 0x01000)
+#define MCM_DBCR (CFG_CCSRBAR + 0x01008)
+
+/*
* l2cr values. Look in config_<BOARD>.h for the actual setup
*/
#define l2cr 1017
#define L2CR_HWF 0x00000800 /* bit 20 - hardware flush */
#define L2CR_L2IP 0x00000001 /* global invalidate in progress */
-/*----------------------------------------------------------------
+/*
* BAT settings. Look in config_<BOARD>.h for the actual setup
*/
#ifndef __ASSEMBLY__
-typedef struct
-{
- unsigned long freqProcessor;
- unsigned long freqSystemBus;
+typedef struct {
+ unsigned long freqProcessor;
+ unsigned long freqSystemBus;
} MPC86xx_SYS_INFO;
#define l1icache_enable icache_enable
#endif /* _ASMLANGUAGE */
#endif /* __MPC86xx_H__ */
-
-