arm64: zynqmp: Handle CONFIG_BOARD_LATE_INIT via Kconfig

[platform/kernel/u-boot.git] / include / mpc83xx.h

diff --git a/include/mpc83xx.h b/include/mpc83xx.h
index b295d6d..a4c5bd3 100644 (file)
--- a/include/mpc83xx.h
+++ b/include/mpc83xx.h
@@ -1,13 +1,6 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
 /*
  * Copyright (C) 2004-2007, 2010 Freescale Semiconductor, Inc.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
  */
 
 #ifndef __MPC83XX_H__
@@ -1117,6 +1110,8 @@
 #define CSBNDS_EA                      0x000000FF
 #define CSBNDS_EA_SHIFT                        24
 
+#ifndef CONFIG_MPC83XX_SDRAM
+
 /*
  * CSn_CONFIG - Chip Select Configuration Register
  */
@@ -1303,7 +1298,6 @@
  */
 #define SDRAM_INTERVAL_REFINT          0x3FFF0000
 #define SDRAM_INTERVAL_REFINT_SHIFT    16
-#define SDRAM_INTERVAL_BSTOPRE         0x00003FFF
 #define SDRAM_INTERVAL_BSTOPRE_SHIFT   0
 
 /*
@@ -1415,6 +1409,8 @@
 #define ECC_ERROR_MAN_SBEC             (0xff000000 >> 24)
 #define ECC_ERROR_MAN_SBEC_SHIFT       0
 
+#endif /* !CONFIG_MPC83XX_SDRAM */
+
 /*
  * CONFIG_ADDRESS - PCI Config Address Register
  */
@@ -1518,6 +1514,7 @@
  */
 #define PMCCR1_POWER_OFF               0x00000020
 
+#ifndef CONFIG_RAM
 /*
  * DDRCDR - DDR Control Driver Register
  */
@@ -1539,6 +1536,7 @@
 #define DDRCDR_DDR_CFG         0x00040000
 #define DDRCDR_M_ODR           0x00000002
 #define DDRCDR_Q_DRN           0x00000001
+#endif /* !CONFIG_RAM */
 
 /*
  * PCIE Bridge Register