Merge branch 'inka4x0-ng' of /home/m8/git/u-boot/

[platform/kernel/u-boot.git] / include / mpc83xx.h

diff --git a/include/mpc83xx.h b/include/mpc83xx.h
index 60fc214..4d32c6a 100644 (file)
--- a/include/mpc83xx.h
+++ b/include/mpc83xx.h
@@ -25,6 +25,7 @@
 /* System reset offset (PowerPC standard)
  */
 #define EXC_OFF_SYS_RESET              0x0100
+#define        _START_OFFSET                   EXC_OFF_SYS_RESET
 
 /* IMMRBAR - Internal Memory Register Base Address
  */
@@ -85,6 +86,8 @@
 #define SPR_8360_REV12                 0x80490012
 #define SPR_8360E_REV20                        0x80480020
 #define SPR_8360_REV20                 0x80490020
+#define SPR_8360E_REV21                        0x80480021
+#define SPR_8360_REV21                 0x80490021
 
 #define SPR_8323E_REV10                        0x80620010
 #define SPR_8323_REV10                 0x80630010
@@ -438,9 +441,9 @@
 #define HRCWH_ROM_LOC_LOCAL_32BIT      0x00700000
 
 #if defined(CONFIG_MPC831X)
-#define HRCWH_ROM_LOC_NAND_SP_8BIT     0x00100000
+#define HRCWH_ROM_LOC_NAND_SP_8BIT     0x00100000
 #define HRCWH_ROM_LOC_NAND_SP_16BIT    0x00200000
-#define HRCWH_ROM_LOC_NAND_LP_8BIT     0x00500000
+#define HRCWH_ROM_LOC_NAND_LP_8BIT     0x00500000
 #define HRCWH_ROM_LOC_NAND_LP_16BIT    0x00600000
 
 #define HRCWH_RL_EXT_LEGACY            0x00000000
@@ -599,7 +602,9 @@
 #define SCCR_TSEC1CM_3                 0xC0000000
 
 #define SCCR_TSEC1ON                   0x20000000
+#define SCCR_TSEC1ON_SHIFT             29
 #define SCCR_TSEC2ON                   0x10000000
+#define SCCR_TSEC2ON_SHIFT             28
 
 #endif
 
@@ -700,8 +705,9 @@
 #define SDRAM_CFG_SREN                 0x40000000
 #define SDRAM_CFG_ECC_EN               0x20000000
 #define SDRAM_CFG_RD_EN                        0x10000000
-#define SDRAM_CFG_SDRAM_TYPE           0x03000000
-#define SDRAM_CFG_SDRAM_TYPE_DDR       0x02000000
+#define SDRAM_CFG_SDRAM_TYPE_DDR1      0x02000000
+#define SDRAM_CFG_SDRAM_TYPE_DDR2      0x03000000
+#define SDRAM_CFG_SDRAM_TYPE_MASK      0x07000000
 #define SDRAM_CFG_SDRAM_TYPE_SHIFT     24
 #define SDRAM_CFG_DYN_PWR              0x00200000
 #define SDRAM_CFG_32_BE                        0x00080000
@@ -1217,7 +1223,7 @@
 #define FCR_CMD1               0x00FF0000
 #define FCR_CMD1_SHIFT         16
 #define FCR_CMD2               0x0000FF00
-#define FCR_CMD2_SHIFT         8
+#define FCR_CMD2_SHIFT         8
 #define FCR_CMD3               0x000000FF
 #define FCR_CMD3_SHIFT         0
 
@@ -1241,8 +1247,8 @@
 /* LTESR - Transfer Error Status Register
  */
 #define LTESR_BM               0x80000000
-#define LTESR_FCT              0x40000000
-#define LTESR_PAR              0x20000000
+#define LTESR_FCT              0x40000000
+#define LTESR_PAR              0x20000000
 #define LTESR_WP               0x04000000
 #define LTESR_ATMW             0x00800000
 #define LTESR_ATMR             0x00400000