mpc83xx: Introduce ARCH_MPC832*

[platform/kernel/u-boot.git] / include / mpc83xx.h

diff --git a/include/mpc83xx.h b/include/mpc83xx.h
index b295d6d..0f4466a 100644 (file)
--- a/include/mpc83xx.h
+++ b/include/mpc83xx.h
@@ -1,13 +1,6 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
 /*
  * Copyright (C) 2004-2007, 2010 Freescale Semiconductor, Inc.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
  */
 
 #ifndef __MPC83XX_H__
@@ -136,7 +129,7 @@
 #define SPCR_TSEC2EP                   0x00000003
 #define SPCR_TSEC2EP_SHIFT             (31-31)
 
-#elif defined(CONFIG_MPC8308) || defined(CONFIG_MPC831x) || \
+#elif defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC831X) || \
        defined(CONFIG_MPC837x)
 /* SPCR bits - MPC8308, MPC831x and MPC837x specific */
 /* TSEC data priority */
@@ -215,7 +208,7 @@
 #define SICRH_UC2E1OBI                 0x00000002
 #define SICRH_UC2E2OBI                 0x00000001
 
-#elif defined(CONFIG_MPC832x)
+#elif defined(CONFIG_ARCH_MPC832X)
 /* SICRL bits - MPC832x specific */
 #define SICRL_LDP_LCS_A                        0x80000000
 #define SICRL_IRQ_CKS                  0x20000000
@@ -223,7 +216,7 @@
 #define SICRL_URT_CTPR                 0x06000000
 #define SICRL_IRQ_CTPR                 0x00C00000
 
-#elif defined(CONFIG_MPC8313)
+#elif defined(CONFIG_ARCH_MPC8313)
 /* SICRL bits - MPC8313 specific */
 #define SICRL_LBC                      0x30000000
 #define SICRL_UART                     0x0C000000
@@ -255,7 +248,7 @@
 #define SICRH_TSOBI1                   0x00000002
 #define SICRH_TSOBI2                   0x00000001
 
-#elif defined(CONFIG_MPC8315)
+#elif defined(CONFIG_ARCH_MPC8315)
 /* SICRL bits - MPC8315 specific */
 #define SICRL_DMA_CH0                  0xc0000000
 #define SICRL_DMA_SPI                  0x30000000
@@ -343,7 +336,7 @@
 #define SICRH_SPI                      0x00000003
 #define SICRH_SPI_SD                   0x00000001
 
-#elif defined(CONFIG_MPC8308)
+#elif defined(CONFIG_ARCH_MPC8308)
 /* SICRL bits - MPC8308 specific */
 #define SICRL_SPI_PF0                  (0 << 28)
 #define SICRL_SPI_PF1                  (1 << 28)
@@ -391,7 +384,7 @@
 #define SICRH_TSOBI2_V3P3              (0 << 0)
 #define SICRH_TSOBI2_V2P5              (1 << 0)
 
-#elif defined(CONFIG_MPC8309)
+#elif defined(CONFIG_ARCH_MPC8309)
 /* SICR_1 */
 #define SICR_1_UART1_UART1S            (0 << (30-2))
 #define SICR_1_UART1_UART1RTS          (1 << (30-2))
@@ -600,7 +593,7 @@
 #define HRCWL_CORE_TO_CSB_2_5X1                0x00050000
 #define HRCWL_CORE_TO_CSB_3X1          0x00060000
 
-#if defined(CONFIG_MPC8360) || defined(CONFIG_MPC832x)
+#if defined(CONFIG_MPC8360) || defined(CONFIG_ARCH_MPC832X)
 #define HRCWL_CEVCOD                   0x000000C0
 #define HRCWL_CEVCOD_SHIFT             6
 #define HRCWL_CE_PLL_VCO_DIV_4         0x00000000
@@ -646,7 +639,7 @@
 #define HRCWL_CE_TO_PLL_1X30           0x0000001E
 #define HRCWL_CE_TO_PLL_1X31           0x0000001F
 
-#elif defined(CONFIG_MPC8308) || defined(CONFIG_MPC8315)
+#elif defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC8315)
 #define HRCWL_SVCOD                    0x30000000
 #define HRCWL_SVCOD_SHIFT              28
 #define HRCWL_SVCOD_DIV_2              0x00000000
@@ -661,7 +654,7 @@
 #define HRCWL_SVCOD_DIV_8              0x10000000
 #define HRCWL_SVCOD_DIV_2              0x20000000
 #define HRCWL_SVCOD_DIV_1              0x30000000
-#elif defined(CONFIG_MPC8309)
+#elif defined(CONFIG_ARCH_MPC8309)
 
 #define HRCWL_CEVCOD                   0x000000C0
 #define HRCWL_CEVCOD_SHIFT             6
@@ -772,7 +765,7 @@
 #define HRCWH_ROM_LOC_LOCAL_16BIT      0x00600000
 #define HRCWH_ROM_LOC_LOCAL_32BIT      0x00700000
 
-#if defined(CONFIG_MPC8308) || defined(CONFIG_MPC831x) || \
+#if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC831X) || \
        defined(CONFIG_MPC837x)
 #define HRCWH_ROM_LOC_NAND_SP_8BIT     0x00100000
 #define HRCWH_ROM_LOC_NAND_SP_16BIT    0x00200000
@@ -825,7 +818,7 @@
 /*
  * RSR - Reset Status Register
  */
-#if defined(CONFIG_MPC8308) || defined(CONFIG_MPC831x) || \
+#if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC831X) || \
        defined(CONFIG_MPC837x)
 #define RSR_RSTSRC                     0xF0000000      /* Reset source */
 #define RSR_RSTSRC_SHIFT               28
@@ -972,7 +965,7 @@
 #define SCCR_USBCM_2                   0x00A00000
 #define SCCR_USBCM_3                   0x00F00000
 
-#elif defined(CONFIG_MPC8313)
+#elif defined(CONFIG_ARCH_MPC8313)
 /* TSEC1 bits are for TSEC2 as well */
 #define SCCR_TSEC1CM                   0xc0000000
 #define SCCR_TSEC1CM_SHIFT             30
@@ -993,7 +986,7 @@
 #define SCCR_USBDRCM_2                 0x00200000
 #define SCCR_USBDRCM_3                 0x00300000
 
-#elif defined(CONFIG_MPC8308) || defined(CONFIG_MPC8315)
+#elif defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC8315)
 /* SCCR bits - MPC8315/MPC8308 specific */
 #define SCCR_TSEC1CM                   0xc0000000
 #define SCCR_TSEC1CM_SHIFT             30
@@ -1078,7 +1071,7 @@
 #define SCCR_SATACM_1                  0x00000055
 #define SCCR_SATACM_2                  0x000000aa
 #define SCCR_SATACM_3                  0x000000ff
-#elif defined(CONFIG_MPC8309)
+#elif defined(CONFIG_ARCH_MPC8309)
 /* SCCR bits - MPC8309 specific */
 #define SCCR_SDHCCM                    0x0c000000
 #define SCCR_SDHCCM_SHIFT              26
@@ -1117,12 +1110,14 @@
 #define CSBNDS_EA                      0x000000FF
 #define CSBNDS_EA_SHIFT                        24
 
+#ifndef CONFIG_MPC83XX_SDRAM
+
 /*
  * CSn_CONFIG - Chip Select Configuration Register
  */
 #define CSCONFIG_EN                    0x80000000
 #define CSCONFIG_AP                    0x00800000
-#if defined(CONFIG_MPC830x) || defined(CONFIG_MPC831x)
+#if defined(CONFIG_ARCH_MPC830X) || defined(CONFIG_ARCH_MPC831X)
 #define CSCONFIG_ODT_RD_NEVER          0x00000000
 #define CSCONFIG_ODT_RD_ONLY_CURRENT   0x00100000
 #define CSCONFIG_ODT_RD_ONLY_OTHER_CS  0x00200000
@@ -1131,7 +1126,7 @@
 #define CSCONFIG_ODT_WR_ONLY_CURRENT   0x00010000
 #define CSCONFIG_ODT_WR_ONLY_OTHER_CS  0x00020000
 #define CSCONFIG_ODT_WR_ALL            0x00040000
-#elif defined(CONFIG_MPC832x)
+#elif defined(CONFIG_ARCH_MPC832X)
 #define CSCONFIG_ODT_RD_CFG            0x00400000
 #define CSCONFIG_ODT_WR_CFG            0x00040000
 #elif defined(CONFIG_MPC8360) || defined(CONFIG_MPC837x)
@@ -1244,14 +1239,14 @@
 #define SDRAM_CFG_SDRAM_TYPE_MASK      0x07000000
 #define SDRAM_CFG_SDRAM_TYPE_SHIFT     24
 #define SDRAM_CFG_DYN_PWR              0x00200000
-#if defined(CONFIG_MPC8308) || defined(CONFIG_MPC831x)
+#if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC831X)
 #define SDRAM_CFG_DBW_MASK             0x00180000
 #define SDRAM_CFG_DBW_16               0x00100000
 #define SDRAM_CFG_DBW_32               0x00080000
 #else
 #define SDRAM_CFG_32_BE                        0x00080000
 #endif
-#if !defined(CONFIG_MPC8308)
+#if !defined(CONFIG_ARCH_MPC8308)
 #define SDRAM_CFG_8_BE                 0x00040000
 #endif
 #define SDRAM_CFG_NCAP                 0x00020000
@@ -1303,7 +1298,6 @@
  */
 #define SDRAM_INTERVAL_REFINT          0x3FFF0000
 #define SDRAM_INTERVAL_REFINT_SHIFT    16
-#define SDRAM_INTERVAL_BSTOPRE         0x00003FFF
 #define SDRAM_INTERVAL_BSTOPRE_SHIFT   0
 
 /*
@@ -1415,6 +1409,8 @@
 #define ECC_ERROR_MAN_SBEC             (0xff000000 >> 24)
 #define ECC_ERROR_MAN_SBEC_SHIFT       0
 
+#endif /* !CONFIG_MPC83XX_SDRAM */
+
 /*
  * CONFIG_ADDRESS - PCI Config Address Register
  */
@@ -1518,6 +1514,7 @@
  */
 #define PMCCR1_POWER_OFF               0x00000020
 
+#ifndef CONFIG_RAM
 /*
  * DDRCDR - DDR Control Driver Register
  */
@@ -1539,6 +1536,7 @@
 #define DDRCDR_DDR_CFG         0x00040000
 #define DDRCDR_M_ODR           0x00000002
 #define DDRCDR_Q_DRN           0x00000001
+#endif /* !CONFIG_RAM */
 
 /*
  * PCIE Bridge Register