nvme: implement multiple I/O Command Set support

[platform/kernel/linux-starfive.git] / include / linux / nvme.h

diff --git a/include/linux/nvme.h b/include/linux/nvme.h
index 5ce51ab..81ffe52 100644 (file)
--- a/include/linux/nvme.h
+++ b/include/linux/nvme.h
@@ -132,6 +132,7 @@ enum {
 #define NVME_CAP_TIMEOUT(cap)  (((cap) >> 24) & 0xff)
 #define NVME_CAP_STRIDE(cap)   (((cap) >> 32) & 0xf)
 #define NVME_CAP_NSSRC(cap)    (((cap) >> 36) & 0x1)
+#define NVME_CAP_CSS(cap)      (((cap) >> 37) & 0xff)
 #define NVME_CAP_MPSMIN(cap)   (((cap) >> 48) & 0xf)
 #define NVME_CAP_MPSMAX(cap)   (((cap) >> 52) & 0xf)
 
@@ -162,7 +163,6 @@ enum {
 
 enum {
        NVME_CC_ENABLE          = 1 << 0,
-       NVME_CC_CSS_NVM         = 0 << 4,
        NVME_CC_EN_SHIFT        = 0,
        NVME_CC_CSS_SHIFT       = 4,
        NVME_CC_MPS_SHIFT       = 7,
@@ -170,6 +170,9 @@ enum {
        NVME_CC_SHN_SHIFT       = 14,
        NVME_CC_IOSQES_SHIFT    = 16,
        NVME_CC_IOCQES_SHIFT    = 20,
+       NVME_CC_CSS_NVM         = 0 << NVME_CC_CSS_SHIFT,
+       NVME_CC_CSS_CSI         = 6 << NVME_CC_CSS_SHIFT,
+       NVME_CC_CSS_MASK        = 7 << NVME_CC_CSS_SHIFT,
        NVME_CC_AMS_RR          = 0 << NVME_CC_AMS_SHIFT,
        NVME_CC_AMS_WRRU        = 1 << NVME_CC_AMS_SHIFT,
        NVME_CC_AMS_VS          = 7 << NVME_CC_AMS_SHIFT,
@@ -179,6 +182,8 @@ enum {
        NVME_CC_SHN_MASK        = 3 << NVME_CC_SHN_SHIFT,
        NVME_CC_IOSQES          = NVME_NVM_IOSQES << NVME_CC_IOSQES_SHIFT,
        NVME_CC_IOCQES          = NVME_NVM_IOCQES << NVME_CC_IOCQES_SHIFT,
+       NVME_CAP_CSS_NVM        = 1 << 0,
+       NVME_CAP_CSS_CSI        = 1 << 6,
        NVME_CSTS_RDY           = 1 << 0,
        NVME_CSTS_CFS           = 1 << 1,
        NVME_CSTS_NSSRO         = 1 << 4,
@@ -374,6 +379,8 @@ enum {
        NVME_ID_CNS_CTRL                = 0x01,
        NVME_ID_CNS_NS_ACTIVE_LIST      = 0x02,
        NVME_ID_CNS_NS_DESC_LIST        = 0x03,
+       NVME_ID_CNS_CS_NS               = 0x05,
+       NVME_ID_CNS_CS_CTRL             = 0x06,
        NVME_ID_CNS_NS_PRESENT_LIST     = 0x10,
        NVME_ID_CNS_NS_PRESENT          = 0x11,
        NVME_ID_CNS_CTRL_NS_LIST        = 0x12,
@@ -384,6 +391,10 @@ enum {
 };
 
 enum {
+       NVME_CSI_NVM                    = 0,
+};
+
+enum {
        NVME_DIR_IDENTIFY               = 0x00,
        NVME_DIR_STREAMS                = 0x01,
        NVME_DIR_SND_ID_OP_ENABLE       = 0x01,
@@ -435,11 +446,13 @@ struct nvme_ns_id_desc {
 #define NVME_NIDT_EUI64_LEN    8
 #define NVME_NIDT_NGUID_LEN    16
 #define NVME_NIDT_UUID_LEN     16
+#define NVME_NIDT_CSI_LEN      1
 
 enum {
        NVME_NIDT_EUI64         = 0x01,
        NVME_NIDT_NGUID         = 0x02,
        NVME_NIDT_UUID          = 0x03,
+       NVME_NIDT_CSI           = 0x04,
 };
 
 struct nvme_smart_log {
@@ -972,7 +985,9 @@ struct nvme_identify {
        __u8                    cns;
        __u8                    rsvd3;
        __le16                  ctrlid;
-       __u32                   rsvd11[5];
+       __u8                    rsvd11[3];
+       __u8                    csi;
+       __u32                   rsvd12[4];
 };
 
 #define NVME_IDENTIFY_DATA_SIZE 4096