Merge tag 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/rdma/rdma

[platform/kernel/linux-starfive.git] / include / linux / mlx5 / mlx5_ifc.h

diff --git a/include/linux/mlx5/mlx5_ifc.h b/include/linux/mlx5/mlx5_ifc.h
index 47241eb..6d16eed 100644 (file)
--- a/include/linux/mlx5/mlx5_ifc.h
+++ b/include/linux/mlx5/mlx5_ifc.h
@@ -438,11 +438,11 @@ struct mlx5_ifc_flow_table_prop_layout_bits {
        u8         reserved_at_60[0x18];
        u8         log_max_ft_num[0x8];
 
-       u8         reserved_at_80[0x18];
+       u8         reserved_at_80[0x10];
+       u8         log_max_flow_counter[0x8];
        u8         log_max_destination[0x8];
 
-       u8         log_max_flow_counter[0x8];
-       u8         reserved_at_a8[0x10];
+       u8         reserved_at_a0[0x18];
        u8         log_max_flow[0x8];
 
        u8         reserved_at_c0[0x40];
@@ -623,7 +623,19 @@ struct mlx5_ifc_fte_match_set_misc3_bits {
 
        u8         geneve_tlv_option_0_data[0x20];
 
-       u8         reserved_at_140[0xc0];
+       u8         gtpu_teid[0x20];
+
+       u8         gtpu_msg_type[0x8];
+       u8         gtpu_msg_flags[0x8];
+       u8         reserved_at_170[0x10];
+
+       u8         gtpu_dw_2[0x20];
+
+       u8         gtpu_first_ext_dw_0[0x20];
+
+       u8         gtpu_dw_0[0x20];
+
+       u8         reserved_at_1e0[0x20];
 };
 
 struct mlx5_ifc_fte_match_set_misc4_bits {
@@ -950,7 +962,9 @@ struct mlx5_ifc_roce_cap_bits {
        u8         roce_apm[0x1];
        u8         reserved_at_1[0x3];
        u8         sw_r_roce_src_udp_port[0x1];
-       u8         reserved_at_5[0x19];
+       u8         fl_rc_qp_when_roce_disabled[0x1];
+       u8         fl_rc_qp_when_roce_enabled[0x1];
+       u8         reserved_at_7[0x17];
        u8         qp_ts_format[0x2];
 
        u8         reserved_at_20[0x60];
@@ -1242,9 +1256,17 @@ enum {
 
 enum {
        MLX5_FLEX_PARSER_GENEVE_ENABLED         = 1 << 3,
+       MLX5_FLEX_PARSER_MPLS_OVER_GRE_ENABLED  = 1 << 4,
+       mlx5_FLEX_PARSER_MPLS_OVER_UDP_ENABLED  = 1 << 5,
        MLX5_FLEX_PARSER_VXLAN_GPE_ENABLED      = 1 << 7,
        MLX5_FLEX_PARSER_ICMP_V4_ENABLED        = 1 << 8,
        MLX5_FLEX_PARSER_ICMP_V6_ENABLED        = 1 << 9,
+       MLX5_FLEX_PARSER_GENEVE_TLV_OPTION_0_ENABLED = 1 << 10,
+       MLX5_FLEX_PARSER_GTPU_ENABLED           = 1 << 11,
+       MLX5_FLEX_PARSER_GTPU_DW_2_ENABLED      = 1 << 16,
+       MLX5_FLEX_PARSER_GTPU_FIRST_EXT_DW_0_ENABLED = 1 << 17,
+       MLX5_FLEX_PARSER_GTPU_DW_0_ENABLED      = 1 << 18,
+       MLX5_FLEX_PARSER_GTPU_TEID_ENABLED      = 1 << 19,
 };
 
 enum {
@@ -1302,7 +1324,9 @@ struct mlx5_ifc_cmd_hca_cap_bits {
        u8         log_max_srq_sz[0x8];
        u8         log_max_qp_sz[0x8];
        u8         event_cap[0x1];
-       u8         reserved_at_91[0x7];
+       u8         reserved_at_91[0x2];
+       u8         isolate_vl_tc_new[0x1];
+       u8         reserved_at_94[0x4];
        u8         prio_tag_required[0x1];
        u8         reserved_at_99[0x2];
        u8         log_max_qp[0x5];
@@ -1642,7 +1666,9 @@ struct mlx5_ifc_cmd_hca_cap_bits {
        u8         cqe_compression_timeout[0x10];
        u8         cqe_compression_max_num[0x10];
 
-       u8         reserved_at_5e0[0x10];
+       u8         reserved_at_5e0[0x8];
+       u8         flex_parser_id_gtpu_dw_0[0x4];
+       u8         reserved_at_5ec[0x4];
        u8         tag_matching[0x1];
        u8         rndv_offload_rc[0x1];
        u8         rndv_offload_dc[0x1];
@@ -1653,7 +1679,8 @@ struct mlx5_ifc_cmd_hca_cap_bits {
        u8         affiliate_nic_vport_criteria[0x8];
        u8         native_port_num[0x8];
        u8         num_vhca_ports[0x8];
-       u8         reserved_at_618[0x6];
+       u8         flex_parser_id_gtpu_teid[0x4];
+       u8         reserved_at_61c[0x2];
        u8         sw_owner_id[0x1];
        u8         reserved_at_61f[0x1];
 
@@ -1688,7 +1715,8 @@ struct mlx5_ifc_cmd_hca_cap_bits {
        u8         reserved_at_6e0[0x10];
        u8         sf_base_id[0x10];
 
-       u8         reserved_at_700[0x8];
+       u8         flex_parser_id_gtpu_dw_2[0x4];
+       u8         flex_parser_id_gtpu_first_ext_dw_0[0x4];
        u8         num_total_dynamic_vf_msix[0x18];
        u8         reserved_at_720[0x14];
        u8         dynamic_msix_table_size[0xc];
@@ -2923,7 +2951,8 @@ struct mlx5_ifc_qpc_bits {
        u8         state[0x4];
        u8         lag_tx_port_affinity[0x4];
        u8         st[0x8];
-       u8         reserved_at_10[0x3];
+       u8         reserved_at_10[0x2];
+       u8         isolate_vl_tc[0x1];
        u8         pm_state[0x2];
        u8         reserved_at_15[0x1];
        u8         req_e2e_credit_mode[0x2];
@@ -8852,6 +8881,8 @@ struct mlx5_ifc_pplm_reg_bits {
 
        u8         fec_override_admin_100g_2x[0x10];
        u8         fec_override_admin_50g_1x[0x10];
+
+       u8         reserved_at_140[0x140];
 };
 
 struct mlx5_ifc_ppcnt_reg_bits {
@@ -9959,6 +9990,53 @@ struct mlx5_ifc_mirc_reg_bits {
        u8         reserved_at_20[0x20];
 };
 
+struct mlx5_ifc_pddr_monitor_opcode_bits {
+       u8         reserved_at_0[0x10];
+       u8         monitor_opcode[0x10];
+};
+
+union mlx5_ifc_pddr_troubleshooting_page_status_opcode_auto_bits {
+       struct mlx5_ifc_pddr_monitor_opcode_bits pddr_monitor_opcode;
+       u8         reserved_at_0[0x20];
+};
+
+enum {
+       /* Monitor opcodes */
+       MLX5_PDDR_REG_TRBLSH_GROUP_OPCODE_MONITOR = 0x0,
+};
+
+struct mlx5_ifc_pddr_troubleshooting_page_bits {
+       u8         reserved_at_0[0x10];
+       u8         group_opcode[0x10];
+
+       union mlx5_ifc_pddr_troubleshooting_page_status_opcode_auto_bits status_opcode;
+
+       u8         reserved_at_40[0x20];
+
+       u8         status_message[59][0x20];
+};
+
+union mlx5_ifc_pddr_reg_page_data_auto_bits {
+       struct mlx5_ifc_pddr_troubleshooting_page_bits pddr_troubleshooting_page;
+       u8         reserved_at_0[0x7c0];
+};
+
+enum {
+       MLX5_PDDR_REG_PAGE_SELECT_TROUBLESHOOTING_INFO_PAGE      = 0x1,
+};
+
+struct mlx5_ifc_pddr_reg_bits {
+       u8         reserved_at_0[0x8];
+       u8         local_port[0x8];
+       u8         pnat[0x2];
+       u8         reserved_at_12[0xe];
+
+       u8         reserved_at_20[0x18];
+       u8         page_select[0x8];
+
+       union mlx5_ifc_pddr_reg_page_data_auto_bits page_data;
+};
+
 union mlx5_ifc_ports_control_registers_document_bits {
        struct mlx5_ifc_bufferx_reg_bits bufferx_reg;
        struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout;
@@ -9973,6 +10051,9 @@ union mlx5_ifc_ports_control_registers_document_bits {
        struct mlx5_ifc_pamp_reg_bits pamp_reg;
        struct mlx5_ifc_paos_reg_bits paos_reg;
        struct mlx5_ifc_pcap_reg_bits pcap_reg;
+       struct mlx5_ifc_pddr_monitor_opcode_bits pddr_monitor_opcode;
+       struct mlx5_ifc_pddr_reg_bits pddr_reg;
+       struct mlx5_ifc_pddr_troubleshooting_page_bits pddr_troubleshooting_page;
        struct mlx5_ifc_peir_reg_bits peir_reg;
        struct mlx5_ifc_pelc_reg_bits pelc_reg;
        struct mlx5_ifc_pfcc_reg_bits pfcc_reg;
@@ -10220,7 +10301,7 @@ struct mlx5_ifc_pbmc_reg_bits {
 
        struct mlx5_ifc_bufferx_reg_bits buffer[10];
 
-       u8         reserved_at_2e0[0x40];
+       u8         reserved_at_2e0[0x80];
 };
 
 struct mlx5_ifc_qtct_reg_bits {