Merge tag 'xilinx-for-v2022.01-rc3' of https://source.denx.de/u-boot/custodians/u...

[platform/kernel/u-boot.git] / include / linux / clk-provider.h

diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h
index 0ef6e68..9d296f2 100644 (file)
--- a/include/linux/clk-provider.h
+++ b/include/linux/clk-provider.h
@@ -9,11 +9,12 @@
 #ifndef __LINUX_CLK_PROVIDER_H
 #define __LINUX_CLK_PROVIDER_H
 
-#include <dm.h>
 #include <linux/bitops.h>
 #include <linux/err.h>
 #include <clk-uclass.h>
 
+struct udevice;
+
 static inline void clk_dm(ulong id, struct clk *clk)
 {
        if (!IS_ERR(clk))
@@ -74,6 +75,19 @@ struct clk_mux {
 extern const struct clk_ops clk_mux_ops;
 u8 clk_mux_get_parent(struct clk *clk);
 
+/**
+ * clk_mux_index_to_val() - Convert the parent index to the register value
+ *
+ * It returns the value to write in the hardware register to output the selected
+ * input clock parent.
+ *
+ * @table: array of register values corresponding to the parent index (optional)
+ * @flags: hardware-specific flags
+ * @index: parent clock index
+ * @return the register value
+ */
+unsigned int clk_mux_index_to_val(u32 *table, unsigned int flags, u8 index);
+
 struct clk_gate {
        struct clk      clk;
        void __iomem    *reg;
@@ -123,6 +137,50 @@ struct clk_divider {
 #define CLK_DIVIDER_READ_ONLY          BIT(5)
 #define CLK_DIVIDER_MAX_AT_ZERO                BIT(6)
 extern const struct clk_ops clk_divider_ops;
+
+/**
+ * clk_divider_get_table_div() - convert the register value to the divider
+ *
+ * @table:  array of register values corresponding to valid dividers
+ * @val: value to convert
+ * @return the divider
+ */
+unsigned int clk_divider_get_table_div(const struct clk_div_table *table,
+                                      unsigned int val);
+
+/**
+ * clk_divider_get_table_val() - convert the divider to the register value
+ *
+ * It returns the value to write in the hardware register to divide the input
+ * clock rate by @div.
+ *
+ * @table: array of register values corresponding to valid dividers
+ * @div: requested divider
+ * @return the register value
+ */
+unsigned int clk_divider_get_table_val(const struct clk_div_table *table,
+                                      unsigned int div);
+
+/**
+ * clk_divider_is_valid_div() - check if the divider is valid
+ *
+ * @table: array of valid dividers (optional)
+ * @div: divider to check
+ * @flags: hardware-specific flags
+ * @return true if the divider is valid, false otherwise
+ */
+bool clk_divider_is_valid_div(const struct clk_div_table *table,
+                             unsigned int div, unsigned long flags);
+
+/**
+ * clk_divider_is_valid_table_div - check if the divider is in the @table array
+ *
+ * @table: array of valid dividers
+ * @div: divider to check
+ * @return true if the divider is found in the @table array, false otherwise
+ */
+bool clk_divider_is_valid_table_div(const struct clk_div_table *table,
+                                   unsigned int div);
 unsigned long divider_recalc_rate(struct clk *hw, unsigned long parent_rate,
                                  unsigned int val,
                                  const struct clk_div_table *table,
@@ -134,6 +192,8 @@ struct clk_fixed_factor {
        unsigned int    div;
 };
 
+extern const struct clk_ops clk_fixed_rate_ops;
+
 #define to_clk_fixed_factor(_clk) container_of(_clk, struct clk_fixed_factor,\
                                               clk)
 
@@ -142,7 +202,10 @@ struct clk_fixed_rate {
        unsigned long fixed_rate;
 };
 
-#define to_clk_fixed_rate(dev) ((struct clk_fixed_rate *)dev_get_platdata(dev))
+#define to_clk_fixed_rate(dev) ((struct clk_fixed_rate *)dev_get_plat(dev))
+
+void clk_fixed_rate_ofdata_to_plat_(struct udevice *dev,
+                                   struct clk_fixed_rate *plat);
 
 struct clk_composite {
        struct clk      clk;
@@ -184,11 +247,11 @@ struct clk *clk_register_mux(struct device *dev, const char *name,
                void __iomem *reg, u8 shift, u8 width,
                u8 clk_mux_flags);
 
+struct clk *clk_register_fixed_rate(struct device *dev, const char *name,
+                                   ulong rate);
+
 const char *clk_hw_get_name(const struct clk *hw);
 ulong clk_generic_get_rate(struct clk *clk);
 
-static inline struct clk *dev_get_clk_ptr(struct udevice *dev)
-{
-       return (struct clk *)dev_get_uclass_priv(dev);
-}
+struct clk *dev_get_clk_ptr(struct udevice *dev);
 #endif /* __LINUX_CLK_PROVIDER_H */