u32 hp_stat; /* 0x08 SEC_MON_HP Status Register */
};
-#define HPCOMR_SW_SV 0x100 /* Security Violation bit */
-#define HPCOMR_SW_FSV 0x200 /* Fatal Security Violation bit */
-#define HPCOMR_SSM_ST 0x1 /* SSM_ST field in SEC_MON command */
+#define HPCOMR_SW_SV 0x100 /* Security Violation bit */
+#define HPCOMR_SW_FSV 0x200 /* Fatal Security Violation bit */
+#define HPCOMR_SSM_ST 0x1 /* SSM_ST field in SEC_MON command */
+#define HPCOMR_SSM_ST_DIS 0x2 /* Disable Secure to Trusted State */
+#define HPCOMR_SSM_SFNS_DIS 0x4 /* Disable Soft Fail to Non-Secure */
#define HPSR_SSM_ST_CHECK 0x900 /* SEC_MON is in check state */
#define HPSR_SSM_ST_NON_SECURE 0xb00 /* SEC_MON is in non secure state */
#define HPSR_SSM_ST_TRUST 0xd00 /* SEC_MON is in trusted state */
#define HPSR_SSM_ST_SOFT_FAIL 0x300 /* SEC_MON is in soft fail state */
+#define HPSR_SSM_ST_SECURE 0xf00 /* SEC_MON is in secure state */
#define HPSR_SSM_ST_MASK 0xf00 /* Mask for SSM_ST field */
/*
SEC_MON_SW_SV,
};
-int change_sec_mon_state(uint32_t initial_state, uint32_t final_state);
+/* Transition SEC_MON state */
+int set_sec_mon_state(u32 state);
#endif /* __FSL_SEC_MON_H */