global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace

[platform/kernel/u-boot.git] / include / fsl_sec.h

diff --git a/include/fsl_sec.h b/include/fsl_sec.h
index dca0dd0..d8861d1 100644 (file)
--- a/include/fsl_sec.h
+++ b/include/fsl_sec.h
@@ -3,7 +3,7 @@
  * Common internal memory map for some Freescale SoCs
  *
  * Copyright 2014 Freescale Semiconductor, Inc.
- * Copyright 2018 NXP
+ * Copyright 2018, 2021 NXP
  */
 
 #ifndef __FSL_SEC_H
@@ -28,6 +28,8 @@
 #error Neither CONFIG_SYS_FSL_SEC_LE nor CONFIG_SYS_FSL_SEC_BE is defined
 #endif
 
+#define BLOB_SIZE(x)           ((x) + 32 + 16) /* Blob buffer size */
+
 /* Security Engine Block (MS = Most Sig., LS = Least Sig.) */
 #if CONFIG_SYS_FSL_SEC_COMPAT >= 4
 /* RNG4 TRNG test registers */
@@ -46,7 +48,11 @@ struct rng4tst {
        u32 rtmctl;             /* misc. control register */
        u32 rtscmisc;           /* statistical check misc. register */
        u32 rtpkrrng;           /* poker range register */
-#define RTSDCTL_ENT_DLY_MIN    3200
+#ifdef CONFIG_MX6SX
+#define RTSDCTL_ENT_DLY                12000
+#else
+#define RTSDCTL_ENT_DLY                3200
+#endif
 #define RTSDCTL_ENT_DLY_MAX    12800
        union {
                u32 rtpkrmax;   /* PRGM=1: poker max. limit register */
@@ -192,12 +198,10 @@ typedef struct ccsr_sec {
 #define SEC_CHAVID_LS_RNG_SHIFT                16
 #define SEC_CHAVID_RNG_LS_MASK         0x000f0000
 
-#define CONFIG_JRSTARTR_JR0            0x00000001
-
 struct jr_regs {
 #if defined(CONFIG_SYS_FSL_SEC_LE) && \
        !(defined(CONFIG_MX6) || defined(CONFIG_MX7) || \
-         defined(CONFIG_MX7ULP) || defined(CONFIG_IMX8M))
+         defined(CONFIG_MX7ULP) || defined(CONFIG_IMX8M) || defined(CONFIG_IMX8))
        u32 irba_l;
        u32 irba_h;
 #else
@@ -212,7 +216,7 @@ struct jr_regs {
        u32 irja;
 #if defined(CONFIG_SYS_FSL_SEC_LE) && \
        !(defined(CONFIG_MX6) || defined(CONFIG_MX7) || \
-         defined(CONFIG_MX7ULP) || defined(CONFIG_IMX8M))
+         defined(CONFIG_MX7ULP) || defined(CONFIG_IMX8M) || defined(CONFIG_IMX8))
        u32 orba_l;
        u32 orba_h;
 #else
@@ -246,7 +250,7 @@ struct jr_regs {
 struct sg_entry {
 #if defined(CONFIG_SYS_FSL_SEC_LE) && \
        !(defined(CONFIG_MX6) || defined(CONFIG_MX7) || \
-         defined(CONFIG_MX7ULP) || defined(CONFIG_IMX8M))
+         defined(CONFIG_MX7ULP) || defined(CONFIG_IMX8M) || defined(CONFIG_IMX8))
        uint32_t addr_lo;       /* Memory Address - lo */
        uint32_t addr_hi;       /* Memory Address of start of buffer - hi */
 #else
@@ -265,18 +269,17 @@ struct sg_entry {
 #define SG_ENTRY_OFFSET_SHIFT  0
 };
 
-#define BLOB_SIZE(x)           ((x) + 32 + 16) /* Blob buffer size */
-
 #if defined(CONFIG_MX6) || defined(CONFIG_MX7) || \
-       defined(CONFIG_MX7ULP) || defined(CONFIG_IMX8M)
+       defined(CONFIG_MX7ULP) || defined(CONFIG_IMX8M) || defined(CONFIG_IMX8)
 /* Job Ring Base Address */
-#define JR_BASE_ADDR(x) (CONFIG_SYS_FSL_SEC_ADDR + 0x1000 * (x + 1))
+#define JR_BASE_ADDR(x) (CFG_SYS_FSL_SEC_ADDR + 0x1000 * (x + 1))
 /* Secure Memory Offset varies accross versions */
 #define SM_V1_OFFSET 0x0f4
 #define SM_V2_OFFSET 0xa00
 /*Secure Memory Versioning */
 #define SMVID_V2 0x20105
-#define SM_VERSION(x)  (x < SMVID_V2 ? 1 : 2)
+#define SM_VERSION(x)  ({typeof(x) _x = x; \
+               _x < SMVID_V2 ? 1 : (_x < 0x20300 ? 2 : 3); })
 #define SM_OFFSET(x)  (x == 1 ? SM_V1_OFFSET : SM_V2_OFFSET)
 /* CAAM Job Ring 0 Registers */
 /* Secure Memory Partition Owner register */
@@ -284,7 +287,7 @@ struct sg_entry {
 /* JR Allocation Error */
 #define SMCSJR_AERR            (3 << 12)
 /* Secure memory partition 0 page 0 owner register */
-#define CAAM_SMPO_0        (CONFIG_SYS_FSL_SEC_ADDR + 0x1FBC)
+#define CAAM_SMPO_0        (CFG_SYS_FSL_SEC_ADDR + 0x1FBC)
 /* Secure memory command register */
 #define CAAM_SMCJR(v, jr)   (JR_BASE_ADDR(jr) + SM_OFFSET(v) + SM_CMD(v))
 /* Secure memory command status register */
@@ -303,8 +306,10 @@ struct sg_entry {
 #define SM_CMD(v)              (v == 1 ? 0x0 : 0x1E4)
 #define SM_STATUS(v)           (v == 1 ? 0x8 : 0x1EC)
 #define SM_PERM(v)             (v == 1 ?  0x10 : 0x4)
-#define SM_GROUP2(v)           (v == 1 ? 0x14 : 0x8)
-#define SM_GROUP1(v)           (v == 1 ? 0x18 : 0xC)
+#define SM_GROUP2(v)           ({typeof(v) _v = v; \
+               _v == 1 ? 0x14 : (_v == 2 ? 0x8 : 0xC); })
+#define SM_GROUP1(v)           ({typeof(v) _v = v; \
+               _v == 1 ? 0x18 : (_v == 2 ? 0xC : 0x8); })
 #define CMD_PAGE_ALLOC         0x1
 #define CMD_PAGE_DEALLOC       0x2
 #define CMD_PART_DEALLOC       0x3
@@ -322,10 +327,15 @@ struct sg_entry {
 #define SEC_MEM_PAGE2          (CAAM_ARB_BASE_ADDR + 0x2000)
 #define SEC_MEM_PAGE3          (CAAM_ARB_BASE_ADDR + 0x3000)
 
-#define JR_MID                 2               /* Matches ROM configuration */
-#define KS_G1                  (1 << JR_MID)   /* CAAM only */
-#define PERM                   0x0000B008      /* Clear on release, lock SMAP
-                                                * lock SMAG group 1 Blob */
+#ifdef CONFIG_IMX8M
+#define JR_MID    (1)         /* Matches ATF configuration */
+#define KS_G1     (0x10000 << JR_MID) /* CAAM only */
+#define PERM      (0xB080)    /* CSP, SMAP_LCK, SMAG_LCK, G1_BLOB */
+#else
+#define JR_MID    (2)         /* Matches ROM configuration */
+#define KS_G1     BIT(JR_MID) /* CAAM only */
+#define PERM      (0xB008)    /* CSP, SMAP_LCK, SMAG_LCK, G1_BLOB */
+#endif /* CONFIG_IMX8M */
 
 /* HAB WRAPPED KEY header */
 #define WRP_HDR_SIZE           0x08