configs: Re-sync HUSH options

[platform/kernel/u-boot.git] / include / fsl_ddr_sdram.h

diff --git a/include/fsl_ddr_sdram.h b/include/fsl_ddr_sdram.h
index 095b33e..cf316a4 100644 (file)
--- a/include/fsl_ddr_sdram.h
+++ b/include/fsl_ddr_sdram.h
@@ -1,9 +1,7 @@
 /*
  * Copyright 2008-2014 Freescale Semiconductor, Inc.
  *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * Version 2 as published by the Free Software Foundation.
+ * SPDX-License-Identifier:    GPL-2.0
  */
 
 #ifndef FSL_DDR_MEMCTL_H
@@ -33,6 +31,15 @@
 #define DDR3_RTT_20_OHM                4 /* RTT_Nom = RZQ/12 */
 #define DDR3_RTT_30_OHM                5 /* RTT_Nom = RZQ/8 */
 
+#define DDR4_RTT_OFF           0
+#define DDR4_RTT_60_OHM                1       /* RZQ/4 */
+#define DDR4_RTT_120_OHM       2       /* RZQ/2 */
+#define DDR4_RTT_40_OHM                3       /* RZQ/6 */
+#define DDR4_RTT_240_OHM       4       /* RZQ/1 */
+#define DDR4_RTT_48_OHM                5       /* RZQ/5 */
+#define DDR4_RTT_80_OHM                6       /* RZQ/3 */
+#define DDR4_RTT_34_OHM                7       /* RZQ/7 */
+
 #define DDR2_RTT_OFF           0
 #define DDR2_RTT_75_OHM                1
 #define DDR2_RTT_150_OHM       2
@@ -116,12 +123,14 @@ typedef struct ddr4_spd_eeprom_s generic_spd_eeprom_t;
 
 #define SDRAM_CFG2_FRC_SR              0x80000000
 #define SDRAM_CFG2_D_INIT              0x00000010
+#define SDRAM_CFG2_AP_EN               0x00000020
 #define SDRAM_CFG2_ODT_CFG_MASK                0x00600000
 #define SDRAM_CFG2_ODT_NEVER           0
 #define SDRAM_CFG2_ODT_ONLY_WRITE      1
 #define SDRAM_CFG2_ODT_ONLY_READ       2
 #define SDRAM_CFG2_ODT_ALWAYS          3
 
+#define SDRAM_INTERVAL_BSTOPRE 0x3FFF
 #define TIMING_CFG_2_CPO_MASK  0x0F800000
 
 #if defined(CONFIG_SYS_FSL_DDR_VER) && \
@@ -155,6 +164,8 @@ typedef struct ddr4_spd_eeprom_s generic_spd_eeprom_t;
 #define MD_CNTL_CKE_CNTL_HIGH  0x00200000
 #define MD_CNTL_WRCW           0x00080000
 #define MD_CNTL_MD_VALUE(x)    (x & 0x0000FFFF)
+#define MD_CNTL_CS_SEL(x)      (((x) & 0x7) << 28)
+#define MD_CNTL_MD_SEL(x)      (((x) & 0xf) << 24)
 
 /* DDR_CDR1 */
 #define DDR_CDR1_DHC_EN        0x80000000
@@ -165,6 +176,15 @@ typedef struct ddr4_spd_eeprom_s generic_spd_eeprom_t;
 #define DDR_CDR2_ODT(x) (x & DDR_CDR2_ODT_MASK)
 #define DDR_CDR2_VREF_OVRD(x)  (0x00008080 | ((((x) - 37) & 0x3F) << 8))
 #define DDR_CDR2_VREF_TRAIN_EN 0x00000080
+#define DDR_CDR2_VREF_RANGE_2  0x00000040
+
+/* DDR ERR_DISABLE */
+#define DDR_ERR_DISABLE_APED   (1 << 8)  /* Address parity error disable */
+
+/* Mode Registers */
+#define DDR_MR5_CA_PARITY_LAT_4_CLK    0x1 /* for DDR4-1600/1866/2133 */
+#define DDR_MR5_CA_PARITY_LAT_5_CLK    0x2 /* for DDR4-2400 */
+
 
 #if (defined(CONFIG_SYS_FSL_DDR_VER) && \
        (CONFIG_SYS_FSL_DDR_VER >= FSL_DDR_VER_4_7))
@@ -321,6 +341,8 @@ typedef struct memctl_options_s {
        unsigned int dqs_config;        /* Use DQS? maybe only with DDR2? */
        /* SREN - self-refresh during sleep */
        unsigned int self_refresh_in_sleep;
+       /* SR_IE - Self-refresh interrupt enable */
+       unsigned int self_refresh_interrupt_en;
        unsigned int dynamic_power;     /* DYN_PWR */
        /* memory data width to use (16-bit, 32-bit, 64-bit) */
        unsigned int data_bus_width;
@@ -330,7 +352,7 @@ typedef struct memctl_options_s {
        /* mirrior DIMMs for DDR3 */
        unsigned int mirrored_dimm;
        unsigned int quad_rank_present;
-       unsigned int ap_en;     /* address parity enable for RDIMM */
+       unsigned int ap_en;     /* address parity enable for RDIMM/DDR4-UDIMM */
        unsigned int x4_en;     /* enable x4 devices */
 
        /* Global Timing Parameters */