+/* SPDX-License-Identifier: GPL-2.0 */
/*
- * Copyright 2008-2014 Freescale Semiconductor, Inc.
- *
- * SPDX-License-Identifier: GPL-2.0
+ * Copyright 2008-2016 Freescale Semiconductor, Inc.
+ * Copyright 2017-2018 NXP Semiconductor
*/
#ifndef FSL_DDR_MEMCTL_H
/* DDR_CDR1 */
#define DDR_CDR1_DHC_EN 0x80000000
+#define DDR_CDR1_V0PT9_EN 0x40000000
#define DDR_CDR1_ODT_SHIFT 17
#define DDR_CDR1_ODT_MASK 0x6
#define DDR_CDR2_ODT_MASK 0x1
unsigned int ddr_cdr2;
unsigned int err_disable;
unsigned int err_int_en;
- unsigned int debug[32];
+ unsigned int debug[64];
} fsl_ddr_cfg_regs_t;
typedef struct memctl_options_partial_s {
unsigned int quad_rank_present;
unsigned int ap_en; /* address parity enable for RDIMM/DDR4-UDIMM */
unsigned int x4_en; /* enable x4 devices */
+ unsigned int package_3ds;
/* Global Timing Parameters */
unsigned int cas_latency_override;
unsigned int additive_latency_override_value;
unsigned int clk_adjust; /* */
- unsigned int cpo_override;
+ unsigned int cpo_override; /* override timing_cfg_2[CPO]*/
+ unsigned int cpo_sample; /* optimize debug_29[24:31] */
unsigned int write_data_delay; /* DQS adjust */
unsigned int cswl_override;
unsigned int rcw_override;
unsigned int rcw_1;
unsigned int rcw_2;
+ unsigned int rcw_3;
/* control register 1 */
unsigned int ddr_cdr1;
unsigned int ddr_cdr2;
int max_freq;
fsl_ddr_cfg_regs_t *ddr_settings;
} fixed_ddr_parm_t;
+
+/**
+ * fsl_initdram() - Set up the SDRAM
+ *
+ * @return 0 if OK, -ve on error
+ */
+int fsl_initdram(void);
+
#endif