#define JH7110_E2_IRQ_SYNC_CLK_CORE 324
#define JH7110_STG_CRG_PCLK 325
#define JH7110_STG_SYSCON_PCLK 326
+#define JH7110_STG_APB 327
-#define JH7110_CLK_STG_END 327
+#define JH7110_CLK_STG_END 328
/* aon other */
-#define JH7110_U0_GMAC5_CLK_PTP 327
-#define JH7110_U0_GMAC5_CLK_RMII 328
-#define JH7110_AON_SYSCON_PCLK 329
-#define JH7110_AON_IOMUX_PCLK 330
-#define JH7110_AON_CRG_PCLK 331
-#define JH7110_PMU_CLK_APB 332
-#define JH7110_PMU_CLK_WKUP 333
-#define JH7110_RTC_HMS_CLK_OSC32K_G 334
-#define JH7110_32K_OUT 335
-#define JH7110_RESET0_CTRL_CLK_SRC 336
+#define JH7110_U0_GMAC5_CLK_PTP 328
+#define JH7110_U0_GMAC5_CLK_RMII 329
+#define JH7110_AON_SYSCON_PCLK 330
+#define JH7110_AON_IOMUX_PCLK 331
+#define JH7110_AON_CRG_PCLK 332
+#define JH7110_PMU_CLK_APB 333
+#define JH7110_PMU_CLK_WKUP 334
+#define JH7110_RTC_HMS_CLK_OSC32K_G 335
+#define JH7110_32K_OUT 336
+#define JH7110_RESET0_CTRL_CLK_SRC 337
/* aon other and source */
-#define JH7110_PCLK_MUX_FUNC_PCLK 337
-#define JH7110_PCLK_MUX_BIST_PCLK 338
+#define JH7110_PCLK_MUX_FUNC_PCLK 338
+#define JH7110_PCLK_MUX_BIST_PCLK 339
-#define JH7110_CLK_END 339
+#define JH7110_CLK_END 340
#endif /* __DT_BINDINGS_CLOCK_STARFIVE_JH7110_H__ */