dt-bindings: clock: samsung: remove define with number of clocks

[platform/kernel/linux-starfive.git] / include / dt-bindings / clock / samsung,exynosautov9.h

diff --git a/include/dt-bindings/clock/samsung,exynosautov9.h b/include/dt-bindings/clock/samsung,exynosautov9.h
index 42133af..3065375 100644 (file)
--- a/include/dt-bindings/clock/samsung,exynosautov9.h
+++ b/include/dt-bindings/clock/samsung,exynosautov9.h
@@ -166,16 +166,12 @@
 #define GOUT_CLKCMU_PERIC1_IP          248
 #define GOUT_CLKCMU_PERIS_BUS          249
 
-#define TOP_NR_CLK                     250
-
 /* CMU_BUSMC */
 #define CLK_MOUT_BUSMC_BUS_USER                1
 #define CLK_DOUT_BUSMC_BUSP            2
 #define CLK_GOUT_BUSMC_PDMA0_PCLK      3
 #define CLK_GOUT_BUSMC_SPDMA_PCLK      4
 
-#define BUSMC_NR_CLK                   5
-
 /* CMU_CORE */
 #define CLK_MOUT_CORE_BUS_USER         1
 #define CLK_DOUT_CORE_BUSP             2
@@ -183,8 +179,6 @@
 #define CLK_GOUT_CORE_CCI_PCLK         4
 #define CLK_GOUT_CORE_CMU_CORE_PCLK    5
 
-#define CORE_NR_CLK                    6
-
 /* CMU_FSYS0 */
 #define CLK_MOUT_FSYS0_BUS_USER                1
 #define CLK_MOUT_FSYS0_PCIE_USER       2
@@ -226,8 +220,6 @@
 #define CLK_GOUT_FSYS0_PCIE_GEN3A_4L_CLK               35
 #define CLK_GOUT_FSYS0_PCIE_GEN3B_4L_CLK               36
 
-#define FSYS0_NR_CLK                   37
-
 /* CMU_FSYS1 */
 #define FOUT_MMC_PLL                           1
 
@@ -251,8 +243,6 @@
 #define CLK_GOUT_FSYS1_USB30_0_ACLK            17
 #define CLK_GOUT_FSYS1_USB30_1_ACLK            18
 
-#define FSYS1_NR_CLK                           19
-
 /* CMU_FSYS2 */
 #define CLK_MOUT_FSYS2_BUS_USER                1
 #define CLK_MOUT_FSYS2_UFS_EMBD_USER   2
@@ -262,8 +252,6 @@
 #define CLK_GOUT_FSYS2_UFS_EMBD1_ACLK  6
 #define CLK_GOUT_FSYS2_UFS_EMBD1_UNIPRO        7
 
-#define FSYS2_NR_CLK                   8
-
 /* CMU_PERIC0 */
 #define CLK_MOUT_PERIC0_BUS_USER       1
 #define CLK_MOUT_PERIC0_IP_USER                2
@@ -308,8 +296,6 @@
 #define CLK_GOUT_PERIC0_PCLK_10                42
 #define CLK_GOUT_PERIC0_PCLK_11                43
 
-#define PERIC0_NR_CLK                  44
-
 /* CMU_PERIC1 */
 #define CLK_MOUT_PERIC1_BUS_USER       1
 #define CLK_MOUT_PERIC1_IP_USER                2
@@ -354,14 +340,10 @@
 #define CLK_GOUT_PERIC1_PCLK_10                42
 #define CLK_GOUT_PERIC1_PCLK_11                43
 
-#define PERIC1_NR_CLK                  44
-
 /* CMU_PERIS */
 #define CLK_MOUT_PERIS_BUS_USER                1
 #define CLK_GOUT_SYSREG_PERIS_PCLK     2
 #define CLK_GOUT_WDT_CLUSTER0          3
 #define CLK_GOUT_WDT_CLUSTER1          4
 
-#define PERIS_NR_CLK                   5
-
 #endif /* _DT_BINDINGS_CLOCK_EXYNOSAUTOV9_H */