Merge tag 'backport/v3.14.24-ltsi-rc1/phy-rcar-gen2-usb-to-v3.15' into backport/v3...

[platform/adaptation/renesas_rcar/renesas_kernel.git] / include / dt-bindings / clock / r8a7791-clock.h

diff --git a/include/dt-bindings/clock/r8a7791-clock.h b/include/dt-bindings/clock/r8a7791-clock.h
index 729dc5f..58c3f49 100644 (file)
--- a/include/dt-bindings/clock/r8a7791-clock.h
+++ b/include/dt-bindings/clock/r8a7791-clock.h
@@ -25,6 +25,7 @@
 #define R8A7791_CLK_MSIOF0             0
 
 /* MSTP1 */
+#define R8A7791_CLK_JPU                6
 #define R8A7791_CLK_TMU1               11
 #define R8A7791_CLK_TMU3               21
 #define R8A7791_CLK_TMU2               22
@@ -43,7 +44,8 @@
 #define R8A7791_CLK_SCIFB1             7
 #define R8A7791_CLK_MSIOF1             8
 #define R8A7791_CLK_SCIFB2             16
-#define R8A7791_CLK_DMAC               18
+#define R8A7791_CLK_SYS_DMAC1          18
+#define R8A7791_CLK_SYS_DMAC0          19
 
 /* MSTP3 */
 #define R8A7791_CLK_TPU0               4
@@ -52,6 +54,7 @@
 #define R8A7791_CLK_SDHI0              14
 #define R8A7791_CLK_MMCIF0             15
 #define R8A7791_CLK_IIC0               18
+#define R8A7791_CLK_PCIEC              19
 #define R8A7791_CLK_IIC1               23
 #define R8A7791_CLK_SSUSB              28
 #define R8A7791_CLK_CMT1               29
@@ -63,6 +66,7 @@
 #define R8A7791_CLK_PWM                        23
 
 /* MSTP7 */
+#define R8A7791_CLK_EHCI               3
 #define R8A7791_CLK_HSUSB              4
 #define R8A7791_CLK_HSCIF2             13
 #define R8A7791_CLK_SCIF5              14
@@ -105,6 +109,32 @@
 #define R8A7791_CLK_I2C1               30
 #define R8A7791_CLK_I2C0               31
 
+/* MSTP10 */
+#define R8A7791_CLK_SSI_ALL            5
+#define R8A7791_CLK_SSI9               6
+#define R8A7791_CLK_SSI8               7
+#define R8A7791_CLK_SSI7               8
+#define R8A7791_CLK_SSI6               9
+#define R8A7791_CLK_SSI5               10
+#define R8A7791_CLK_SSI4               11
+#define R8A7791_CLK_SSI3               12
+#define R8A7791_CLK_SSI2               13
+#define R8A7791_CLK_SSI1               14
+#define R8A7791_CLK_SSI0               15
+#define R8A7791_CLK_SCU_ALL            17
+#define R8A7791_CLK_SCU_DVC1           18
+#define R8A7791_CLK_SCU_DVC0           19
+#define R8A7791_CLK_SCU_SRC9           22
+#define R8A7791_CLK_SCU_SRC8           23
+#define R8A7791_CLK_SCU_SRC7           24
+#define R8A7791_CLK_SCU_SRC6           25
+#define R8A7791_CLK_SCU_SRC5           26
+#define R8A7791_CLK_SCU_SRC4           27
+#define R8A7791_CLK_SCU_SRC3           28
+#define R8A7791_CLK_SCU_SRC2           29
+#define R8A7791_CLK_SCU_SRC1           30
+#define R8A7791_CLK_SCU_SRC0           31
+
 /* MSTP11 */
 #define R8A7791_CLK_SCIFA3             6
 #define R8A7791_CLK_SCIFA4             7