Merge tag 'v3.14.25' into backport/v3.14.24-ltsi-rc1+v3.14.25/snapshot-merge.wip

[platform/adaptation/renesas_rcar/renesas_kernel.git] / include / dt-bindings / clock / r8a7790-clock.h

diff --git a/include/dt-bindings/clock/r8a7790-clock.h b/include/dt-bindings/clock/r8a7790-clock.h
index 859e9be..8ea7ab0 100644 (file)
--- a/include/dt-bindings/clock/r8a7790-clock.h
+++ b/include/dt-bindings/clock/r8a7790-clock.h
@@ -26,6 +26,7 @@
 #define R8A7790_CLK_MSIOF0             0
 
 /* MSTP1 */
+#define R8A7790_CLK_JPU                6
 #define R8A7790_CLK_TMU1               11
 #define R8A7790_CLK_TMU3               21
 #define R8A7790_CLK_TMU2               22
@@ -33,8 +34,8 @@
 #define R8A7790_CLK_TMU0               25
 #define R8A7790_CLK_VSP1_DU1           27
 #define R8A7790_CLK_VSP1_DU0           28
-#define R8A7790_CLK_VSP1_RT            30
-#define R8A7790_CLK_VSP1_SY            31
+#define R8A7790_CLK_VSP1_R             30
+#define R8A7790_CLK_VSP1_S             31
 
 /* MSTP2 */
 #define R8A7790_CLK_SCIFA2             2
@@ -46,10 +47,11 @@
 #define R8A7790_CLK_MSIOF1             8
 #define R8A7790_CLK_MSIOF3             15
 #define R8A7790_CLK_SCIFB2             16
-#define R8A7790_CLK_SYS_DMAC0          18
-#define R8A7790_CLK_SYS_DMAC1          19
+#define R8A7790_CLK_SYS_DMAC1          18
+#define R8A7790_CLK_SYS_DMAC0          19
 
 /* MSTP3 */
+#define R8A7790_CLK_IIC2               0
 #define R8A7790_CLK_TPU0               4
 #define R8A7790_CLK_MMCIF1             5
 #define R8A7790_CLK_SDHI3              11
@@ -57,6 +59,9 @@
 #define R8A7790_CLK_SDHI1              13
 #define R8A7790_CLK_SDHI0              14
 #define R8A7790_CLK_MMCIF0             15
+#define R8A7790_CLK_IIC0               18
+#define R8A7790_CLK_PCIEC              19
+#define R8A7790_CLK_IIC1               23
 #define R8A7790_CLK_SSUSB              28
 #define R8A7790_CLK_CMT1               29
 #define R8A7790_CLK_USBDMAC0           30
@@ -104,4 +109,30 @@
 #define R8A7790_CLK_I2C1               30
 #define R8A7790_CLK_I2C0               31
 
+/* MSTP10 */
+#define R8A7790_CLK_SSI_ALL            5
+#define R8A7790_CLK_SSI9               6
+#define R8A7790_CLK_SSI8               7
+#define R8A7790_CLK_SSI7               8
+#define R8A7790_CLK_SSI6               9
+#define R8A7790_CLK_SSI5               10
+#define R8A7790_CLK_SSI4               11
+#define R8A7790_CLK_SSI3               12
+#define R8A7790_CLK_SSI2               13
+#define R8A7790_CLK_SSI1               14
+#define R8A7790_CLK_SSI0               15
+#define R8A7790_CLK_SCU_ALL            17
+#define R8A7790_CLK_SCU_DVC1           18
+#define R8A7790_CLK_SCU_DVC0           19
+#define R8A7790_CLK_SCU_SRC9           22
+#define R8A7790_CLK_SCU_SRC8           23
+#define R8A7790_CLK_SCU_SRC7           24
+#define R8A7790_CLK_SCU_SRC6           25
+#define R8A7790_CLK_SCU_SRC5           26
+#define R8A7790_CLK_SCU_SRC4           27
+#define R8A7790_CLK_SCU_SRC3           28
+#define R8A7790_CLK_SCU_SRC2           29
+#define R8A7790_CLK_SCU_SRC1           30
+#define R8A7790_CLK_SCU_SRC0           31
+
 #endif /* __DT_BINDINGS_CLOCK_R8A7790_H__ */