Merge tag 'drm-misc-next-2020-10-27' of git://anongit.freedesktop.org/drm/drm-misc...
[platform/kernel/linux-starfive.git] / include / drm / drm_dp_helper.h
index ae4e202..1f0ee7f 100644 (file)
@@ -28,6 +28,8 @@
 #include <linux/types.h>
 #include <drm/drm_connector.h>
 
+struct drm_device;
+
 /*
  * Unless otherwise noted, all values are from the DP 1.1a spec.  Note that
  * DP and DPCD versions are independent.  Differences from 1.0 are not noted,
 # define DP_DS_PORT_TYPE_DP_DUALMODE        5
 # define DP_DS_PORT_TYPE_WIRELESS           6
 # define DP_DS_PORT_HPD                            (1 << 3)
+# define DP_DS_NON_EDID_MASK               (0xf << 4)
+# define DP_DS_NON_EDID_720x480i_60        (1 << 4)
+# define DP_DS_NON_EDID_720x480i_50        (2 << 4)
+# define DP_DS_NON_EDID_1920x1080i_60      (3 << 4)
+# define DP_DS_NON_EDID_1920x1080i_50      (4 << 4)
+# define DP_DS_NON_EDID_1280x720_60        (5 << 4)
+# define DP_DS_NON_EDID_1280x720_50        (7 << 4)
 /* offset 1 for VGA is maximum megapixels per second / 8 */
-/* offset 2 */
+/* offset 1 for DVI/HDMI is maximum TMDS clock in Mbps / 2.5 */
+/* offset 2 for VGA/DVI/HDMI */
 # define DP_DS_MAX_BPC_MASK                (3 << 0)
 # define DP_DS_8BPC                        0
 # define DP_DS_10BPC                       1
 # define DP_DS_12BPC                       2
 # define DP_DS_16BPC                       3
+/* offset 3 for DVI */
+# define DP_DS_DVI_DUAL_LINK               (1 << 1)
+# define DP_DS_DVI_HIGH_COLOR_DEPTH        (1 << 2)
+/* offset 3 for HDMI */
+# define DP_DS_HDMI_FRAME_SEQ_TO_FRAME_PACK (1 << 0)
+# define DP_DS_HDMI_YCBCR422_PASS_THROUGH   (1 << 1)
+# define DP_DS_HDMI_YCBCR420_PASS_THROUGH   (1 << 2)
+# define DP_DS_HDMI_YCBCR444_TO_422_CONV    (1 << 3)
+# define DP_DS_HDMI_YCBCR444_TO_420_CONV    (1 << 4)
 
 #define DP_MAX_DOWNSTREAM_PORTS                    0x10
 
 #define DP_CEC_TX_MESSAGE_BUFFER               0x3020
 #define DP_CEC_MESSAGE_BUFFER_LENGTH             0x10
 
+#define DP_PROTOCOL_CONVERTER_CONTROL_0                0x3050 /* DP 1.3 */
+# define DP_HDMI_DVI_OUTPUT_CONFIG             (1 << 0) /* DP 1.3 */
+#define DP_PROTOCOL_CONVERTER_CONTROL_1                0x3051 /* DP 1.3 */
+# define DP_CONVERSION_TO_YCBCR420_ENABLE      (1 << 0) /* DP 1.3 */
+# define DP_HDMI_EDID_PROCESSING_DISABLE       (1 << 1) /* DP 1.4 */
+# define DP_HDMI_AUTONOMOUS_SCRAMBLING_DISABLE (1 << 2) /* DP 1.4 */
+# define DP_HDMI_FORCE_SCRAMBLING              (1 << 3) /* DP 1.4 */
+#define DP_PROTOCOL_CONVERTER_CONTROL_2                0x3052 /* DP 1.3 */
+# define DP_CONVERSION_TO_YCBCR422_ENABLE      (1 << 0) /* DP 1.3 */
+
 /* HDCP 1.3 and HDCP 2.2 */
 #define DP_AUX_HDCP_BKSV               0x68000
 #define DP_AUX_HDCP_RI_PRIME           0x68005
 #define DP_POWER_DOWN_PHY              0x25
 #define DP_SINK_EVENT_NOTIFY           0x30
 #define DP_QUERY_STREAM_ENC_STATUS     0x38
+#define  DP_QUERY_STREAM_ENC_STATUS_STATE_NO_EXIST     0
+#define  DP_QUERY_STREAM_ENC_STATUS_STATE_INACTIVE     1
+#define  DP_QUERY_STREAM_ENC_STATUS_STATE_ACTIVE       2
 
 /* DP 1.2 MST sideband reply types */
 #define DP_SIDEBAND_REPLY_ACK          0x00
 #define DP_MST_PHYSICAL_PORT_0 0
 #define DP_MST_LOGICAL_PORT_0 8
 
+#define DP_LINK_CONSTANT_N_VALUE 0x8000
 #define DP_LINK_STATUS_SIZE       6
 bool drm_dp_channel_eq_ok(const u8 link_status[DP_LINK_STATUS_SIZE],
                          int lane_count);
@@ -1671,13 +1704,35 @@ bool drm_dp_send_real_edid_checksum(struct drm_dp_aux *aux,
 int drm_dp_read_downstream_info(struct drm_dp_aux *aux,
                                const u8 dpcd[DP_RECEIVER_CAP_SIZE],
                                u8 downstream_ports[DP_MAX_DOWNSTREAM_PORTS]);
-int drm_dp_downstream_max_clock(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
-                               const u8 port_cap[4]);
+bool drm_dp_downstream_is_type(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
+                              const u8 port_cap[4], u8 type);
+bool drm_dp_downstream_is_tmds(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
+                              const u8 port_cap[4],
+                              const struct edid *edid);
+int drm_dp_downstream_max_dotclock(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
+                                  const u8 port_cap[4]);
+int drm_dp_downstream_max_tmds_clock(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
+                                    const u8 port_cap[4],
+                                    const struct edid *edid);
+int drm_dp_downstream_min_tmds_clock(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
+                                    const u8 port_cap[4],
+                                    const struct edid *edid);
 int drm_dp_downstream_max_bpc(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
-                             const u8 port_cap[4]);
+                             const u8 port_cap[4],
+                             const struct edid *edid);
+bool drm_dp_downstream_420_passthrough(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
+                                      const u8 port_cap[4]);
+bool drm_dp_downstream_444_to_420_conversion(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
+                                            const u8 port_cap[4]);
+struct drm_display_mode *drm_dp_downstream_mode(struct drm_device *dev,
+                                               const u8 dpcd[DP_RECEIVER_CAP_SIZE],
+                                               const u8 port_cap[4]);
 int drm_dp_downstream_id(struct drm_dp_aux *aux, char id[6]);
-void drm_dp_downstream_debug(struct seq_file *m, const u8 dpcd[DP_RECEIVER_CAP_SIZE],
-                            const u8 port_cap[4], struct drm_dp_aux *aux);
+void drm_dp_downstream_debug(struct seq_file *m,
+                            const u8 dpcd[DP_RECEIVER_CAP_SIZE],
+                            const u8 port_cap[4],
+                            const struct edid *edid,
+                            struct drm_dp_aux *aux);
 enum drm_mode_subconnector
 drm_dp_subconnector_type(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
                         const u8 port_cap[4]);
@@ -1833,7 +1888,7 @@ static inline void drm_dp_cec_unset_edid(struct drm_dp_aux *aux)
  * @link_rate: Requested Link rate from DPCD 0x219
  * @num_lanes: Number of lanes requested by sing through DPCD 0x220
  * @phy_pattern: DP Phy test pattern from DPCD 0x248
- * @hb2_reset: DP HBR2_COMPLIANCE_SCRAMBLER_RESET from DCPD 0x24A and 0x24B
+ * @hbr2_reset: DP HBR2_COMPLIANCE_SCRAMBLER_RESET from DCPD 0x24A and 0x24B
  * @custom80: DP Test_80BIT_CUSTOM_PATTERN from DPCDs 0x250 through 0x259
  * @enhanced_frame_cap: flag for enhanced frame capability.
  */