* (easy to change)
*/
#define CONFIG_CPU_MONAHANS 1 /* Intel Monahan CPU */
+#define CONFIG_CPU_PXA320
#define CONFIG_ZYLONITE 1 /* Zylonite board */
/* #define CONFIG_LCD 1 */
#ifdef CONFIG_LCD
#define CONFIG_SHARP_LM8V31
#endif
-/* #define CONFIG_MMC 1 */
+#undef CONFIG_MMC
#define BOARD_LATE_INIT 1
-#undef CONFIG_SKIP_RELOCATE_UBOOT
#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
+/* we will never enable dcache, because we have to setup MMU first */
+#define CONFIG_SYS_NO_DCACHE
+
/*
* Size of malloc() pool
*/
#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024)
-#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
/*
* Hardware drivers
#undef TURN_ON_ETHERNET
#ifdef TURN_ON_ETHERNET
-# define CONFIG_DRIVER_SMC91111 1
+# define CONFIG_SMC91111 1
# define CONFIG_SMC91111_BASE 0x14000300
# define CONFIG_SMC91111_EXT_PHY
# define CONFIG_SMC_USE_32_BIT
/*
* select serial console configuration
*/
+#define CONFIG_PXA_SERIAL
#define CONFIG_FFUART 1
/* allow to overwrite serial and ethaddr */
#ifdef TURN_ON_ETHERNET
#define CONFIG_CMD_PING
#else
- #define CONFIG_CMD_ENV
+ #define CONFIG_CMD_SAVEENV
#define CONFIG_CMD_NAND
#undef CONFIG_CMD_NET
#define CONFIG_SYS_MEMTEST_START 0x9c000000 /* memtest works on */
#define CONFIG_SYS_MEMTEST_END 0x9c400000 /* 4 ... 8 MB in DRAM */
-#undef CONFIG_SYS_CLKS_IN_HZ /* everything, incl board info, in Hz */
-
#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_DRAM_BASE + 0x8000) /* default load address */
-#define CONFIG_SYS_HZ 3250000 /* incrementer freq: 3.25 MHz */
+#define CONFIG_SYS_HZ 1000
/* Monahans Core Frequency */
#define CONFIG_SYS_MONAHANS_RUN_MODE_OSC_RATIO 16 /* valid values: 8, 16, 24, 31 */
/* valid baudrates */
#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
-/* #define CONFIG_SYS_MMC_BASE 0xF0000000 */
+#ifdef CONFIG_MMC
+#define CONFIG_PXA_MMC
+#define CONFIG_CMD_MMC
+#define CONFIG_SYS_MMC_BASE 0xF0000000
+#endif
/*
* Stack sizes
#undef CONFIG_SYS_SKIP_DRAM_SCRUB
+#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
+#define CONFIG_SYS_INIT_SP_ADDR (GENERATED_GBL_DATA_SIZE + PHYS_SDRAM_1)
/*
* NAND Flash
*/
-#define CONFIG_NEW_NAND_CODE
#define CONFIG_SYS_NAND0_BASE 0x0
#undef CONFIG_SYS_NAND1_BASE
#define CONFIG_MTD_DEBUG
#define CONFIG_MTD_DEBUG_VERBOSE 1
-#define ADDR_COLUMN 1
-#define ADDR_PAGE 2
-#define ADDR_COLUMN_PAGE 3
-
-#define NAND_ChipID_UNKNOWN 0x00
-#define NAND_MAX_FLOORS 1
-#define NAND_MAX_CHIPS 1
-
#define CONFIG_SYS_NO_FLASH 1
#define CONFIG_ENV_IS_IN_NAND 1