#ifndef __CONFIG_H
#define __CONFIG_H
-#define DEBUG
-#undef DEBUG
-
/*-----------------------------------------------------------------------
* High Level Configuration Options
*----------------------------------------------------------------------*/
#define CFG_PERIPHERAL_BASE 0xa0000000 /* internal peripherals */
#define CFG_ISRAM_BASE 0x90000000 /* internal SRAM */
-#define CFG_PCI_MEMBASE 0x80000000 /* mapped pci memory */
-#define CFG_PCI_MEMBASE1 0x90000000 /* mapped pci memory */
-#define CFG_PCI_MEMBASE2 0xa0000000 /* mapped pci memory */
-#define CFG_PCI_MEMBASE3 0xb0000000 /* mapped pci memory */
-
+#define CFG_PCI_MEMBASE 0x80000000 /* mapped PCI memory */
#define CFG_PCI_BASE 0xd0000000 /* internal PCI regs */
-#define CFG_PCI_TARGBASE 0x80000000 /*PCIaddr mapped to CFG_PCI_MEMBASE*/
+#define CFG_PCI_TARGBASE CFG_PCI_MEMBASE
+
+#define CFG_PCIE_MEMBASE 0xb0000000 /* mapped PCIe memory */
+#define CFG_PCIE_MEMSIZE 0x01000000
+#define CFG_PCIE_BASE 0xe0000000 /* PCIe UTL regs */
-/* #define CFG_PCI_BASE_IO 0xB8000000 */ /* internal PCI I-O */
-/* #define CFG_PCI_BASE_REGS 0xBEC00000 */ /* internal PCI regs */
-/* #define CFG_PCI_BASE_CYCLE 0xBED00000 */ /* internal PCI regs */
+#define CFG_PCIE0_CFGBASE 0xc0000000
+#define CFG_PCIE0_XCFGBASE 0xc0000400
+#define CFG_PCIE1_CFGBASE 0xc0001000
+#define CFG_PCIE1_XCFGBASE 0xc0001400
+#define CFG_PCIE2_CFGBASE 0xc0002000
+#define CFG_PCIE2_XCFGBASE 0xc0002400
/* System RAM mapped to PCI space */
#define CONFIG_PCI_SYS_MEM_BUS CFG_SDRAM_BASE
#undef CFG_ENV_IS_IN_EEPROM /* ... not in EEPROM */
#define CONFIG_ENV_OVERWRITE 1
-#define CONFIG_BOOTARGS "console=ttyS0,115200n8 root=/dev/nfs rw"
-#define CONFIG_BOOTCOMMAND "bootm E7C00000" /* autoboot command */
-#define CONFIG_BOOTDELAY -1 /* -1 to disable autoboot */
-
-#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
-#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
+#define CONFIG_PREBOOT "echo;" \
+ "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
+ "echo"
-#define CONFIG_MII 1 /* MII PHY management */
-#undef CONFIG_NET_MULTI
-#define CONFIG_PHY_ADDR 1 /* PHY address, See schematics */
-#define CONFIG_HAS_ETH0
-#define CONFIG_PHY_RESET 1 /* reset phy upon startup */
-#define CONFIG_PHY_RESET_DELAY 1000
-#define CONFIG_CIS8201_PHY 1 /* Enable 'special' RGMII mode for Cicada phy */
-#define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */
-#define CONFIG_NETMASK 255.255.0.0
-#define CONFIG_IPADDR 192.168.80.10
-#define CONFIG_ETHADDR 00:04:AC:01:CA:FE
-#define CFG_RX_ETH_BUFFER 32 /* Number of ethernet rx buffers & descriptors */
-#define CONFIG_SERVERIP 192.168.1.1
+#undef CONFIG_BOOTARGS
#define CONFIG_EXTRA_ENV_SETTINGS \
- "loads_echo=1\0" \
"netdev=eth0\0" \
"hostname=yucca\0" \
"nfsargs=setenv bootargs root=/dev/nfs rw " \
"bootm ${kernel_addr} ${ramdisk_addr}\0" \
"net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \
"bootm\0" \
- "rootpath=/opt/eldk-4.0/ppc_4xx\0" \
+ "rootpath=/opt/eldk/ppc_4xx\0" \
"bootfile=yucca/uImage\0" \
"kernel_addr=E7F10000\0" \
"ramdisk_addr=E7F20000\0" \
"setenv filesize;saveenv\0" \
"upd=run load;run update\0" \
""
+#define CONFIG_BOOTCOMMAND "run flash_self"
-#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \
- CFG_CMD_PCI | \
- CFG_CMD_IRQ | \
- CFG_CMD_I2C | \
+#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
+
+#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
+#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
+
+#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \
+ CFG_CMD_ASKENV | \
+ CFG_CMD_EEPROM | \
CFG_CMD_DHCP | \
- CFG_CMD_PING | \
CFG_CMD_DIAG | \
- CFG_CMD_NET | \
+ CFG_CMD_ELF | \
+ CFG_CMD_I2C | \
+ CFG_CMD_IRQ | \
CFG_CMD_MII | \
- CFG_CMD_EEPROM | \
- CFG_CMD_ELF )
+ CFG_CMD_NET | \
+ CFG_CMD_NFS | \
+ CFG_CMD_PCI | \
+ CFG_CMD_PING | \
+ CFG_CMD_REGINFO | \
+ CFG_CMD_SDRAM )
/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
#include <cmd_confdefs.h>
+#define CONFIG_MII 1 /* MII PHY management */
+#undef CONFIG_NET_MULTI
+#define CONFIG_PHY_ADDR 1 /* PHY address, See schematics */
+#define CONFIG_HAS_ETH0
+#define CONFIG_PHY_RESET 1 /* reset phy upon startup */
+#define CONFIG_PHY_RESET_DELAY 1000
+#define CONFIG_CIS8201_PHY 1 /* Enable 'special' RGMII mode for Cicada phy */
+#define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */
+#define CFG_RX_ETH_BUFFER 32 /* Number of ethernet rx buffers & descriptors */
+
+#define CONFIG_NETCONSOLE /* include NetConsole support */
+#define CONFIG_NET_MULTI /* needed for NetConsole */
+
#undef CONFIG_WATCHDOG /* watchdog disabled */
/*
#define CFG_LOAD_ADDR 0x100000 /* default load address */
#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */
-#define CFG_HZ 1 /* decrementer freq: 1 ms ticks */
+#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
+
+#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
+#define CONFIG_LOOPW 1 /* enable loopw command */
+#define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */
+#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
+#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */
/*-----------------------------------------------------------------------
* FLASH related
*/
/* Support for Intel 82557/82559/82559ER chips. */
#define CONFIG_EEPRO100
+
/*
* For booting Linux, the board info and command line data
* have to be in the first 8 MB of memory, since this is
#define FPGA_REG1C_PE1_WAKE 0x0040
#define FPGA_REG1C_PE2_WAKE 0x0020
#define FPGA_REG1C_PE0_PERST 0x0010
-#define FPGA_REG1C_PE1_PERST 0x0080
-#define FPGA_REG1C_PE2_PERST 0x0040
+#define FPGA_REG1C_PE1_PERST 0x0008
+#define FPGA_REG1C_PE2_PERST 0x0004
/*----------------------------------------------------------------------------+
| Defines
projects / platform / kernel / u-boot.git / blobdiff