ppc4xx: Add fdt support to all remaining AMCC PPC4xx eval boards

[platform/kernel/u-boot.git] / include / configs / yosemite.h

diff --git a/include/configs/yosemite.h b/include/configs/yosemite.h
index 35bce4a..f22e798 100644 (file)
--- a/include/configs/yosemite.h
+++ b/include/configs/yosemite.h
@@ -75,7 +75,7 @@
  *----------------------------------------------------------------------*/
 #define CFG_INIT_RAM_DCACHE    1               /* d-cache as init ram  */
 #define CFG_INIT_RAM_ADDR      0x70000000              /* DCache       */
-#define CFG_INIT_RAM_END       (8 << 10)
+#define CFG_INIT_RAM_END       (4 << 10)
 #define CFG_GBL_DATA_SIZE      256                     /* num bytes initial data*/
 #define CFG_GBL_DATA_OFFSET    (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
 #define CFG_INIT_SP_OFFSET     CFG_GBL_DATA_OFFSET
@@ -139,7 +139,6 @@
 #define CFG_KBYTES_SDRAM        (128 * 1024)    /* 128MB                   */
 #define CFG_SDRAM_BANKS                (2)
 
-
 /*-----------------------------------------------------------------------
  * I2C
  *----------------------------------------------------------------------*/
@@ -160,8 +159,16 @@
 #define CFG_ENV_OFFSET         0x0
 #endif /* CFG_ENV_IS_IN_EEPROM */
 
+/* I2C SYSMON (LM75, AD7414 is almost compatible)                      */
+#define CONFIG_DTT_LM75                1               /* ON Semi's LM75       */
+#define CONFIG_DTT_AD7414      1               /* use AD7414           */
+#define CONFIG_DTT_SENSORS     {0}             /* Sensor addresses     */
+#define CFG_DTT_MAX_TEMP       70
+#define CFG_DTT_LOW_TEMP       -30
+#define CFG_DTT_HYSTERESIS     3
+
 #define CONFIG_PREBOOT "echo;" \
-       "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
+       "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
        "echo"
 
 #undef CONFIG_BOOTARGS
@@ -201,7 +208,7 @@
        "update=protect off fff80000 ffffffff;era fff80000 ffffffff;"   \
                "cp.b 200000 fff80000 80000;"                           \
                "setenv filesize;saveenv\0"                             \
-       "upd=run load;run update\0"                                     \
+       "upd=run load update\0"                                         \
        ""
 #define CONFIG_BOOTCOMMAND     "run flash_self"
 
@@ -219,6 +226,7 @@
 #define CONFIG_MII             1       /* MII PHY management           */
 #define CONFIG_NET_MULTI        1      /* required for netconsole      */
 #define CONFIG_PHY1_ADDR        3
+#define CONFIG_HAS_ETH0                1       /* add support for "ethaddr"    */
 #define CONFIG_HAS_ETH1                1       /* add support for "eth1addr"   */
 #define CONFIG_PHY_ADDR                1       /* PHY address, See schematics  */
 
@@ -273,6 +281,7 @@
 #define CONFIG_CMD_ASKENV
 #define CONFIG_CMD_DHCP
 #define CONFIG_CMD_DIAG
+#define CONFIG_CMD_DTT
 #define CONFIG_CMD_ELF
 #define CONFIG_CMD_EEPROM
 #define CONFIG_CMD_I2C
@@ -361,15 +370,6 @@
 
 #define CFG_BCSR5_PCI66EN      0x80
 
-/*-----------------------------------------------------------------------
- * Cache Configuration
- */
-#define CFG_DCACHE_SIZE                (32<<10) /* For AMCC 440 CPUs                   */
-#define CFG_CACHELINE_SIZE     32      /* ...                  */
-#if defined(CONFIG_CMD_KGDB)
-#define CFG_CACHELINE_SHIFT    5       /* log base 2 of the above value        */
-#endif
-
 /*
  * Internal Definitions
  *
@@ -383,4 +383,8 @@
 #define CONFIG_KGDB_SER_INDEX  2       /* which serial port to use */
 #endif
 
+/* pass open firmware flat tree */
+#define CONFIG_OF_LIBFDT       1
+#define CONFIG_OF_BOARD_SETUP  1
+
 #endif /* __CONFIG_H */