/*===================*/
#if XCHAL_HAVE_PTP_MMU
-#define CONFIG_SYS_MEMORY_BASE \
+#define CFG_SYS_MEMORY_BASE \
(XCHAL_VECBASE_RESET_VADDR - XCHAL_VECBASE_RESET_PADDR)
-#define CONFIG_SYS_IO_BASE 0xf0000000
+#define CFG_SYS_IO_BASE 0xf0000000
#else
-#define CONFIG_SYS_MEMORY_BASE 0x60000000
-#define CONFIG_SYS_IO_BASE 0x90000000
-#define CONFIG_MAX_MEM_MAPPED 0x10000000
+#define CFG_SYS_MEMORY_BASE 0x60000000
+#define CFG_SYS_IO_BASE 0x90000000
+#define CFG_MAX_MEM_MAPPED 0x10000000
#endif
/* Onboard RAM sizes:
*/
#if XCHAL_HAVE_PTP_MMU || CONFIG_BOARD_SDRAM_SIZE < 0x10000000
-#define CONFIG_SYS_SDRAM_SIZE CONFIG_BOARD_SDRAM_SIZE
+#define CFG_SYS_SDRAM_SIZE CONFIG_BOARD_SDRAM_SIZE
#else
-#define CONFIG_SYS_SDRAM_SIZE 0x10000000
+#define CFG_SYS_SDRAM_SIZE 0x10000000
#endif
-#define CONFIG_SYS_SDRAM_BASE MEMADDR(0x00000000)
+#define CFG_SYS_SDRAM_BASE MEMADDR(0x00000000)
/* Lx60 can only map 128kb memory (instead of 256kb) when running under OCD */
-#ifdef CONFIG_XTFPGA_LX60
-# define CONFIG_SYS_MONITOR_LEN 0x00020000 /* 128KB */
-#else
-# define CONFIG_SYS_MONITOR_LEN 0x00040000 /* 256KB */
-#endif
/* Memory test is destructive so default must not overlap vectors or U-Boot*/
-/* Load address for stand-alone applications.
- * MEMADDR cannot be used here, because the definition needs to be
- * a plain number as it's used as -Ttext argument for ld in standalone
- * example makefile.
- * Handle noMMU vs MMUv2 vs MMUv3 distinction here manually.
- */
-#if XCHAL_HAVE_PTP_MMU
-#if XCHAL_VECBASE_RESET_VADDR == XCHAL_VECBASE_RESET_PADDR
-#define CONFIG_STANDALONE_LOAD_ADDR 0x00800000
-#else
-#define CONFIG_STANDALONE_LOAD_ADDR 0xd0800000
-#endif
-#else
-#define CONFIG_STANDALONE_LOAD_ADDR 0x60800000
-#endif
-
-#if defined(CONFIG_MAX_MEM_MAPPED) && \
- CONFIG_MAX_MEM_MAPPED < CONFIG_SYS_SDRAM_SIZE
-#define CONFIG_SYS_MEMORY_SIZE CONFIG_MAX_MEM_MAPPED
+#if defined(CFG_MAX_MEM_MAPPED) && \
+ CFG_MAX_MEM_MAPPED < CFG_SYS_SDRAM_SIZE
+#define XTENSA_SYS_TEXT_ADDR \
+ (MEMADDR(CFG_MAX_MEM_MAPPED) - CONFIG_SYS_MONITOR_LEN)
#else
-#define CONFIG_SYS_MEMORY_SIZE CONFIG_SYS_SDRAM_SIZE
-#endif
-
#define XTENSA_SYS_TEXT_ADDR \
- (MEMADDR(CONFIG_SYS_MEMORY_SIZE) - CONFIG_SYS_MONITOR_LEN)
+ (MEMADDR(CFG_SYS_SDRAM_SIZE) - CONFIG_SYS_MONITOR_LEN)
+#endif
/*==============================*/
/* U-Boot general configuration */
* SHIFT left amount and field WIDTH (bits), and also by a bitMASK.
*/
-/* Date of FPGA bitstream build in binary coded decimal (BCD) */
-#define CONFIG_SYS_FPGAREG_DATE IOADDR(0x0D020000)
-#define FPGAREG_MTH_SHIFT 24 /* BCD month 1..12 */
-#define FPGAREG_MTH_WIDTH 8
-#define FPGAREG_MTH_MASK 0xFF000000
-#define FPGAREG_DAY_SHIFT 16 /* BCD day 1..31 */
-#define FPGAREG_DAY_WIDTH 8
-#define FPGAREG_DAY_MASK 0x00FF0000
-#define FPGAREG_YEAR_SHIFT 0 /* BCD year 2001..9999*/
-#define FPGAREG_YEAR_WIDTH 16
-#define FPGAREG_YEAR_MASK 0x0000FFFF
-
/* FPGA core clock frequency in Hz (also input to UART) */
-#define CONFIG_SYS_FPGAREG_FREQ IOADDR(0x0D020004) /* CPU clock frequency*/
+#define CFG_SYS_FPGAREG_FREQ IOADDR(0x0D020004) /* CPU clock frequency*/
/*
* DIP switch (left=sw1=lsb=bit0, right=sw8=msb=bit7; off=0, on=1):
* Bits 0..5 set the lower 6 bits of the default ethernet MAC.
* Bit 6 is reserved for future use by Tensilica.
- * Bit 7 maps the first 128KB of ROM address space at CONFIG_SYS_ROM_BASE to
+ * Bit 7 maps the first 128KB of ROM address space at CFG_SYS_ROM_BASE to
* the base of flash * (when on/1) or to the base of RAM (when off/0).
*/
-#define CONFIG_SYS_FPGAREG_DIPSW IOADDR(0x0D02000C)
+#define CFG_SYS_FPGAREG_DIPSW IOADDR(0x0D02000C)
#define FPGAREG_MAC_SHIFT 0 /* Ethernet MAC bits 0..5 */
#define FPGAREG_MAC_WIDTH 6
#define FPGAREG_MAC_MASK 0x3f
#define FPGAREG_BOOT_FLASH (1<<FPGAREG_BOOT_SHIFT)
/* Force hard reset of board by writing a code to this register */
-#define CONFIG_SYS_FPGAREG_RESET IOADDR(0x0D020010) /* Reset board .. */
-#define CONFIG_SYS_FPGAREG_RESET_CODE 0x0000DEAD /* by writing this code */
+#define CFG_SYS_FPGAREG_RESET IOADDR(0x0D020010) /* Reset board .. */
+#define CFG_SYS_FPGAREG_RESET_CODE 0x0000DEAD /* by writing this code */
/*====================*/
/* Serial Driver Info */
/*====================*/
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE (-4)
-#define CONFIG_SYS_NS16550_COM1 IOADDR(0x0D050020) /* Base address */
+#define CFG_SYS_NS16550_COM1 IOADDR(0x0D050020) /* Base address */
/* Input clk to NS16550 (in Hz; the SYS_CLK_FREQ is in kHz) */
-#define CONFIG_SYS_NS16550_CLK get_board_sys_clk()
+#define CFG_SYS_NS16550_CLK get_board_sys_clk()
/*======================*/
/* Ethernet Driver Info */
/*======================*/
-#define CONFIG_ETHBASE 00:50:C2:13:6f:00
-#define CONFIG_SYS_ETHOC_BASE IOADDR(0x0d030000)
-#define CONFIG_SYS_ETHOC_BUFFER_ADDR IOADDR(0x0D800000)
+#define CFG_ETHBASE 00:50:C2:13:6f:00
+#define CFG_SYS_ETHOC_BASE IOADDR(0x0d030000)
+#define CFG_SYS_ETHOC_BUFFER_ADDR IOADDR(0x0D800000)
/*=====================*/
/* Flash & Environment */
/*=====================*/
#ifdef CONFIG_XTFPGA_LX60
-# define CONFIG_SYS_FLASH_SIZE 0x0040000 /* 4MB */
-# define CONFIG_SYS_FLASH_SECT_SZ 0x10000 /* block size 64KB */
-# define CONFIG_SYS_FLASH_PARMSECT_SZ 0x2000 /* param size 8KB */
-# define CONFIG_SYS_FLASH_BASE IOADDR(0x08000000)
+# define CFG_SYS_FLASH_SIZE 0x0040000 /* 4MB */
+# define CFG_SYS_FLASH_PARMSECT_SZ 0x2000 /* param size 8KB */
+# define CFG_SYS_FLASH_BASE IOADDR(0x08000000)
#elif defined(CONFIG_XTFPGA_KC705)
-# define CONFIG_SYS_FLASH_SIZE 0x8000000 /* 128MB */
-# define CONFIG_SYS_FLASH_SECT_SZ 0x20000 /* block size 128KB */
-# define CONFIG_SYS_FLASH_PARMSECT_SZ 0x8000 /* param size 32KB */
-# define CONFIG_SYS_FLASH_BASE IOADDR(0x00000000)
+# define CFG_SYS_FLASH_SIZE 0x8000000 /* 128MB */
+# define CFG_SYS_FLASH_PARMSECT_SZ 0x8000 /* param size 32KB */
+# define CFG_SYS_FLASH_BASE IOADDR(0x00000000)
#else
-# define CONFIG_SYS_FLASH_SIZE 0x1000000 /* 16MB */
-# define CONFIG_SYS_FLASH_SECT_SZ 0x20000 /* block size 128KB */
-# define CONFIG_SYS_FLASH_PARMSECT_SZ 0x8000 /* param size 32KB */
-# define CONFIG_SYS_FLASH_BASE IOADDR(0x08000000)
+# define CFG_SYS_FLASH_SIZE 0x1000000 /* 16MB */
+# define CFG_SYS_FLASH_PARMSECT_SZ 0x8000 /* param size 32KB */
+# define CFG_SYS_FLASH_BASE IOADDR(0x08000000)
#endif
-#define CONFIG_SYS_MAX_FLASH_SECT \
- (CONFIG_SYS_FLASH_SECT_SZ/CONFIG_SYS_FLASH_PARMSECT_SZ + \
- CONFIG_SYS_FLASH_SIZE/CONFIG_SYS_FLASH_SECT_SZ - 1)
/*
* Put environment in top block (64kB)
*/
/* print 'E' for empty sector on flinfo */
-#define CONFIG_SYS_FLASH_EMPTY_INFO
#endif /* __CONFIG_H */
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