#define CONFIG_XTFPGA
-/* FPGA CPU freq after init */
-#define CONFIG_SYS_CLK_FREQ (gd->cpu_clk)
-
/*===================*/
/* RAM Layout */
/*===================*/
#define CONFIG_SYS_NS16550_COM1 IOADDR(0x0D050020) /* Base address */
/* Input clk to NS16550 (in Hz; the SYS_CLK_FREQ is in kHz) */
-#define CONFIG_SYS_NS16550_CLK CONFIG_SYS_CLK_FREQ
-#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
+#define CONFIG_SYS_NS16550_CLK get_board_sys_clk()
/*======================*/
/* Ethernet Driver Info */
/*=====================*/
#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
-#define CONFIG_SYS_MAX_FLASH_BANKS 1
#ifdef CONFIG_XTFPGA_LX60
# define CONFIG_SYS_FLASH_SIZE 0x0040000 /* 4MB */
# define CONFIG_SYS_FLASH_SECT_SZ 0x10000 /* block size 64KB */