+/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright (C) 2007-2013 Tensilica, Inc.
* Copyright (C) 2014 - 2016 Cadence Design Systems Inc.
- *
- * SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __CONFIG_H
#define CONFIG_SYS_MEMORY_SIZE CONFIG_SYS_SDRAM_SIZE
#endif
-#define CONFIG_SYS_MEMORY_TOP MEMADDR(CONFIG_SYS_MEMORY_SIZE)
-#define CONFIG_SYS_TEXT_ADDR \
- (CONFIG_SYS_MEMORY_TOP - CONFIG_SYS_MONITOR_LEN)
+#define XTENSA_SYS_TEXT_ADDR \
+ (MEMADDR(CONFIG_SYS_MEMORY_SIZE) - CONFIG_SYS_MONITOR_LEN)
/* Used by tftpboot; env var 'loadaddr' */
#define CONFIG_SYS_LOAD_ADDR MEMADDR(0x02000000)
/*==============================*/
#define CONFIG_BOARD_POSTCLK_INIT
-#define CONFIG_MISC_INIT_R
#define CONFIG_BOOTFILE "uImage"
/* Console I/O Buffer Size */
/* U-Boot autoboot configuration */
/*==============================*/
-#define CONFIG_BOOT_RETRY_TIME 60 /* retry after 60 secs */
-
-#define CONFIG_AUTO_COMPLETE /* Support tab autocompletion */
-#define CONFIG_CMDLINE_EDITING
-#define CONFIG_SYS_LONGHELP
#define CONFIG_MX_CYCLIC
#define CONFIG_SHOW_BOOT_PROGRESS
-#ifdef DEBUG
-#define CONFIG_PANIC_HANG 1 /* Require manual reboot */
-#endif
-
/*=========================================*/
/* FPGA Registers (board info and control) */
/* Input clk to NS16550 (in Hz; the SYS_CLK_FREQ is in kHz) */
#define CONFIG_SYS_NS16550_CLK CONFIG_SYS_CLK_FREQ
-#define CONFIG_CONS_INDEX 1 /* use UART0 for console */
#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
/*======================*/
/* Flash & Environment */
/*=====================*/
-#define CONFIG_SYS_FLASH_CFI
-#define CONFIG_FLASH_CFI_DRIVER /* use generic CFI driver */
#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
#define CONFIG_SYS_MAX_FLASH_BANKS 1
#ifdef CONFIG_XTFPGA_LX60
#define CONFIG_SYS_MAX_FLASH_SECT \
(CONFIG_SYS_FLASH_SECT_SZ/CONFIG_SYS_FLASH_PARMSECT_SZ + \
CONFIG_SYS_FLASH_SIZE/CONFIG_SYS_FLASH_SECT_SZ - 1)
-#define CONFIG_SYS_FLASH_PROTECTION /* hw flash protection */
/*
* Put environment in top block (64kB)