+/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright (C) 2016 NXP Semiconductors
*
* Configuration settings for the i.MX7S Warp board.
- *
- * SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __WARP7_CONFIG_H
#define PHYS_SDRAM_SIZE SZ_512M
-#define CONFIG_MXC_UART_BASE UART1_IPS_BASE_ADDR
+/*
+ * If we have defined the OPTEE ram size and not OPTEE it means that we were
+ * launched by OPTEE, because of that we shall skip all the low level
+ * initialization since it was already done by ATF or OPTEE
+ */
+#ifdef CONFIG_OPTEE_TZDRAM_SIZE
+#ifndef CONFIG_OPTEE
+#define CONFIG_SKIP_LOWLEVEL_INIT
+#endif
+#endif
/* Size of malloc() pool */
#define CONFIG_SYS_MALLOC_LEN (35 * SZ_1M)
/* MMC Config*/
#define CONFIG_SYS_FSL_ESDHC_ADDR USDHC3_BASE_ADDR
-#define CONFIG_SUPPORT_EMMC_BOOT
#define CONFIG_SYS_FSL_ESDHC_HAS_DDR_MODE
#define CONFIG_SYS_MMC_IMG_LOAD_PART 1
#define CONFIG_SERIAL_TAG
#define CONFIG_DFU_ENV_SETTINGS \
- "dfu_alt_info=boot raw 0x2 0x400 mmcpart 1\0" \
+ "dfu_alt_info=boot raw 0x2 0x1000 mmcpart 1\0" \
#define CONFIG_EXTRA_ENV_SETTINGS \
CONFIG_DFU_ENV_SETTINGS \
#define CONFIG_SYS_HZ 1000
/* Physical Memory Map */
-#define CONFIG_NR_DRAM_BANKS 1
#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
/* I2C configs */
-#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_MXC
-#define CONFIG_SYS_I2C_MXC_I2C1
#define CONFIG_SYS_I2C_SPEED 100000
-/* PMIC */
-#define CONFIG_POWER
-#define CONFIG_POWER_I2C
-#define CONFIG_POWER_PFUZE3000
-#define CONFIG_POWER_PFUZE3000_I2C_ADDR 0x08
-
/* environment organization */
#define CONFIG_ENV_SIZE SZ_8K