/* Size of malloc() pool */
#define CONFIG_SYS_MALLOC_LEN (35 * SZ_1M) /* Increase due to DFU */
-#define CONFIG_MXC_UART
#define CONFIG_MXC_UART_BASE UART1_IPS_BASE_ADDR
/* MMC Configs */
#define CONFIG_SYS_FSL_ESDHC_ADDR USDHC2_BASE_ADDR
#define CONFIG_SYS_FSL_ESDHC_HAS_DDR_MODE
-#define CONFIG_SUPPORT_EMMC_BOOT
/* Watchdog */
-#define CONFIG_HW_WATCHDOG
-#define CONFIG_IMX_WATCHDOG
-#define CONFIG_WATCHDOG_TIMEOUT_MSECS 30000 /* 30s */
-
-#define CONFIG_SYS_MEMTEST_START 0x80000000
-#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + SZ_256M)
/* Physical Memory Map */
-#define CONFIG_NR_DRAM_BANKS 1
#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
#define CONFIG_SYS_INIT_SP_ADDR \
(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
-#define CONFIG_ENV_OFFSET (6 * SZ_64K)
-#define CONFIG_ENV_SIZE SZ_8K
-#define CONFIG_SYS_MMC_ENV_DEV 0
-
/* VDD voltage 1.65 - 1.95 */
#define CONFIG_SYS_SD_VOLTAGE 0x00000080