#define CONFIG_SYS_FSL_ESDHC_HAS_DDR_MODE
/* Watchdog */
-#define CONFIG_WATCHDOG_TIMEOUT_MSECS 30000 /* 30s */
-
-#define CONFIG_SYS_MEMTEST_START 0x80000000
-#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + SZ_256M)
/* Physical Memory Map */
#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
#define CONFIG_SYS_INIT_SP_ADDR \
(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
-#define CONFIG_ENV_OFFSET (6 * SZ_64K)
-#define CONFIG_ENV_SIZE SZ_8K
#define CONFIG_SYS_MMC_ENV_DEV 0
/* VDD voltage 1.65 - 1.95 */