#define CONFIG_405GP 1 /* This is a PPC405 CPU */
#define CONFIG_4xx 1 /* ...member of PPC4xx family */
#define CONFIG_WALNUT 1 /* ...on a WALNUT board */
- /* ...and on a SYCAMORE board */
+ /* ...or on a SYCAMORE board */
+
+#define CONFIG_SYS_TEXT_BASE 0xFFFC0000
/*
* Include common defines/options for all AMCC eval boards
* If CONFIG_SYS_405_UART_ERRATA_59 and 200MHz CPU clock,
* set Linux BASE_BAUD to 403200.
*/
-#undef CONFIG_SERIAL_SOFTWARE_FIFO
+#define CONFIG_CONS_INDEX 1 /* Use UART0 */
#undef CONFIG_SYS_EXT_SERIAL_CLOCK /* external serial clock */
#undef CONFIG_SYS_405_UART_ERRATA_59 /* 405GP/CR Rev. D silicon */
#define CONFIG_SYS_BASE_BAUD 691200
#define CONFIG_SYS_INIT_DCACHE_CS 4 /* use cs # 4 for data cache memory */
#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 /* inside of SDRAM */
-#define CONFIG_SYS_INIT_RAM_END 0x2000 /* End of used area in RAM */
-#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_RAM_SIZE 0x2000 /* Size of used area in RAM */
+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
/*-----------------------------------------------------------------------