#undef CONFIG_DDR_32BIT
#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is sys memory*/
-#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_SDRAM_BASE
#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN \
| DDR_SDRAM_CLK_CNTL_CLK_ADJUST_075)
#define CONFIG_DDR_2T_TIMING
#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB */
#define CONFIG_SYS_MALLOC_LEN (256 * 1024) /* Malloc size */
-/*
- * Local Bus LCRR and LBCR regs
- * LCRR: no DLL bypass, Clock divider is 4
- * External Local Bus rate is
- * CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV
- */
-#define CONFIG_SYS_LBC_LBCR 0x00000000
-
#undef CONFIG_SYS_LB_SDRAM /* if board has SDRAM on local bus */
/*