hush.c: Move default CONFIG_SYS_PROMPT_HUSH_PS2 to hush.c

[platform/kernel/u-boot.git] / include / configs / ve8313.h

diff --git a/include/configs/ve8313.h b/include/configs/ve8313.h
index f657610..a587636 100644 (file)
--- a/include/configs/ve8313.h
+++ b/include/configs/ve8313.h
@@ -79,9 +79,10 @@
  * have the SPD connected to I2C.
  */
 #define CONFIG_SYS_DDR_SIZE    128     /* MB */
-#define CONFIG_SYS_DDR_CONFIG  (CSCONFIG_EN \
+#define CONFIG_SYS_DDR_CS0_CONFIG      (CSCONFIG_EN \
                                | CSCONFIG_AP \
-                               | 0x00040000 /* TODO */ \
+                               | CSCONFIG_ODT_RD_NEVER \
+                               | CSCONFIG_ODT_WR_ALL \
                                | CSCONFIG_ROW_BIT_13 \
                                | CSCONFIG_COL_BIT_10)
                                /* 0x80840102 */
@@ -118,7 +119,7 @@
                                /* 0x03202000 */
 #define CONFIG_SYS_SDRAM_CFG   (SDRAM_CFG_SREN \
                                | SDRAM_CFG_SDRAM_TYPE_DDR2 \
-                               | SDRAM_CFG_32_BE)
+                               | SDRAM_CFG_DBW_32)
                                /* 0x43080000 */
 #define CONFIG_SYS_SDRAM_CFG2  0x00401000
 #define CONFIG_SYS_DDR_MODE    ((0x4440 << SDRAM_MODE_ESD_SHIFT) \
@@ -145,18 +146,19 @@
 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE      /* buffer up multiple bytes */
 
 #define CONFIG_SYS_NOR_BR_PRELIM       (CONFIG_SYS_FLASH_BASE \
-                                       | (2 << BR_PS_SHIFT)    /* 16 bit */ \
-                                       | BR_V)                 /* valid */
+                                       | BR_PS_16      /* 16 bit */ \
+                                       | BR_MS_GPCM    /* MSEL = GPCM */ \
+                                       | BR_V)         /* valid */
 #define CONFIG_SYS_NOR_OR_PRELIM       (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
                                        | OR_GPCM_CSNT \
                                        | OR_GPCM_ACS_DIV4 \
                                        | OR_GPCM_SCY_5 \
-                                       | OR_GPCM_TRLX \
+                                       | OR_GPCM_TRLX_SET \
                                        | OR_GPCM_EAD)
                                        /* 0xfe000c55 */
 
 #define CONFIG_SYS_LBLAWBAR0_PRELIM    CONFIG_SYS_FLASH_BASE
-#define CONFIG_SYS_LBLAWAR0_PRELIM     0x80000018 /* 32 MB window size */
+#define CONFIG_SYS_LBLAWAR0_PRELIM     (LBLAWAR_EN | LBLAWAR_32MB)
 
 #define CONFIG_SYS_MAX_FLASH_BANKS     1               /* number of banks */
 #define CONFIG_SYS_MAX_FLASH_SECT      256             /* sectors per dev */
@@ -208,7 +210,7 @@
                                        | BR_MS_FCM             \
                                        | BR_V) /* valid */
                                        /* 0x61000c21 */
-#define CONFIG_SYS_NAND_OR_PRELIM      (0xffff8000 \
+#define CONFIG_SYS_NAND_OR_PRELIM      (OR_AM_32KB \
                                        | OR_FCM_BCTLD \
                                        | OR_FCM_CHT \
                                        | OR_FCM_SCY_2 \
@@ -222,7 +224,7 @@
 #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NAND_OR_PRELIM
 
 #define CONFIG_SYS_LBLAWBAR1_PRELIM    CONFIG_SYS_NAND_BASE
-#define CONFIG_SYS_LBLAWAR1_PRELIM     0x8000000E      /* 32KB  */
+#define CONFIG_SYS_LBLAWAR1_PRELIM     (LBLAWAR_EN | LBLAWAR_32KB)
 
 #define CONFIG_SYS_NAND_LBLAWBAR_PRELIM CONFIG_SYS_LBLAWBAR1_PRELIM
 #define CONFIG_SYS_NAND_LBLAWAR_PRELIM CONFIG_SYS_LBLAWAR1_PRELIM
@@ -232,12 +234,12 @@
                                | BR_PS_8 \
                                | BR_V)
                                /* 0x60000801 */
-#define CONFIG_SYS_OR2_PRELIM  (0xfffe0000 \
+#define CONFIG_SYS_OR2_PRELIM  (OR_AM_128KB \
                                | OR_GPCM_CSNT \
                                | OR_GPCM_XACS \
                                | OR_GPCM_SCY_3 \
-                               | OR_GPCM_TRLX \
-                               | OR_GPCM_EHTR \
+                               | OR_GPCM_TRLX_SET \
+                               | OR_GPCM_EHTR_SET \
                                | OR_GPCM_EAD)
                                /* 0xfffe0937 */
 /* local bus read write buffer mapping SRAM@0x64000000 */
@@ -246,12 +248,12 @@
                                | BR_V)
                                /* 0x62001001 */
 
-#define CONFIG_SYS_OR3_PRELIM  (0xfe000000 \
+#define CONFIG_SYS_OR3_PRELIM  (OR_AM_32MB \
                                | OR_GPCM_CSNT \
                                | OR_GPCM_XACS \
                                | OR_GPCM_SCY_15 \
-                               | OR_GPCM_TRLX \
-                               | OR_GPCM_EHTR \
+                               | OR_GPCM_TRLX_SET \
+                               | OR_GPCM_EHTR_SET \
                                | OR_GPCM_EAD)
                                /* 0xfe0009f7 */
 
@@ -277,7 +279,6 @@
 
 /* Use the HUSH parser */
 #define CONFIG_SYS_HUSH_PARSER
-#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
 
 #if defined(CONFIG_PCI)
 /*