/* Onboard devices */
-#define CONFIG_SYS_MALLOC_LEN 0x100000
+#define CONFIG_SYS_MALLOC_LEN 0x1F0000
#define CONFIG_SYS_LOAD_ADDR 0x00100000
#define CONFIG_SYS_INIT_SP_OFFSET 0x400000
-#define CPU_CLOCK_RATE 500000000 /* Clock for the MIPS core */
-#ifdef CONFIG_SOC_LUTON
+#if defined(CONFIG_SOC_LUTON) || defined(CONFIG_SOC_SERVAL)
+#define CPU_CLOCK_RATE 416666666 /* Clock for the MIPS core */
#define CONFIG_SYS_MIPS_TIMER_FREQ 208333333
#else
+#define CPU_CLOCK_RATE 500000000 /* Clock for the MIPS core */
#define CONFIG_SYS_MIPS_TIMER_FREQ (CPU_CLOCK_RATE / 2)
#endif
#define CONFIG_SYS_NS16550_CLK CONFIG_SYS_MIPS_TIMER_FREQ
#define CONFIG_BOARD_TYPES
-#if defined(CONFIG_ENV_IS_IN_SPI_FLASH) && !defined(CONFIG_ENV_OFFSET)
-#define CONFIG_ENV_OFFSET (1024 * 1024)
-#define CONFIG_ENV_SIZE (256 * 1024)
-#define CONFIG_ENV_SECT_SIZE (256 * 1024)
-
-#define CONFIG_SYS_REDUNDAND_ENVIRONMENT
-#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
-#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SECT_SIZE)
-
-#define CONFIG_ENV_SPI_MAX_HZ 0 /* This force to read from DT */
-#define CONFIG_ENV_SPI_MODE 0 /* This force to read from DT */
-#endif
-
#define CONFIG_SYS_SDRAM_BASE 0x80000000
#if defined(CONFIG_DDRTYPE_H5TQ1G63BFA) || defined(CONFIG_DDRTYPE_MT47H128M8HQ)
#define CONFIG_SYS_SDRAM_SIZE (128 * SZ_1M)
#define CONFIG_CONS_INDEX 1
-#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE
-#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + CONFIG_SYS_SDRAM_SIZE - SZ_1M)
-
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
#define CONFIG_BOARD_EARLY_INIT_R