*
* Configuation settings for the LUBBOCK board.
*
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
+ * SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __CONFIG_H
* High Level Configuration Options
* (easy to change)
*/
-#define CONFIG_PXA27X 1 /* This is an PXA27x CPU */
+#define CONFIG_CPU_PXA27X 1 /* This is an PXA27x CPU */
#define CONFIG_MMC 1
-#define BOARD_LATE_INIT 1
+#define CONFIG_BOARD_LATE_INIT
+#define CONFIG_SYS_TEXT_BASE 0x0
-#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
+/* we will never enable dcache, because we have to setup MMU first */
+#define CONFIG_SYS_DCACHE_OFF
#define RTC
* Size of malloc() pool
*/
#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024)
-#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
/*
* Hardware drivers
/*
* select serial console configuration
*/
-#define CONFIG_SERIAL_MULTI
+#define CONFIG_PXA_SERIAL
#define CONFIG_FFUART 1 /* we use FFUART on Conxs */
#define CONFIG_BTUART 1 /* we use BTUART on Conxs */
#define CONFIG_STUART 1 /* we use STUART on Conxs */
+#define CONFIG_CONS_INDEX 3
/* allow to overwrite serial and ethaddr */
#define CONFIG_ENV_OVERWRITE
*/
#include <config_cmd_default.h>
-#define CONFIG_CMD_MMC
#define CONFIG_CMD_FAT
#define CONFIG_CMD_IMLS
#define CONFIG_CMD_PING
* Miscellaneous configurable options
*/
#define CONFIG_SYS_HUSH_PARSER 1
-#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
#define CONFIG_SYS_LONGHELP /* undef to save memory */
#ifdef CONFIG_SYS_HUSH_PARSER
#define CONFIG_SYS_MEMTEST_START 0xa0400000 /* memtest works on */
#define CONFIG_SYS_MEMTEST_END 0xa0800000 /* 4 ... 8 MB in DRAM */
-#undef CONFIG_SYS_CLKS_IN_HZ /* everything, incl board info, in Hz */
-
#define CONFIG_SYS_LOAD_ADDR 0xa1000000 /* default load address */
-#define CONFIG_SYS_HZ 3686400 /* incrementer freq: 3.6864 MHz */
+#define CONFIG_SYS_HZ 1000
#define CONFIG_SYS_CPUSPEED 0x207 /* need to look more closely, I think this is Turbo = 2x, L=91Mhz */
- /* valid baudrates */
-#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
-
+#ifdef CONFIG_MMC
+#define CONFIG_GENERIC_MMC
+#define CONFIG_PXA_MMC_GENERIC
+#define CONFIG_CMD_MMC
#define CONFIG_SYS_MMC_BASE 0xF0000000
-
-/*
- * Stack sizes
- *
- * The stack sizes are set up in start.S using the settings below
- */
-#define CONFIG_STACKSIZE (128*1024) /* regular stack */
-#ifdef CONFIG_USE_IRQ
-#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */
-#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */
#endif
/*
#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
+#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
+#define CONFIG_SYS_INIT_SP_ADDR (GENERATED_GBL_DATA_SIZE + PHYS_SDRAM_1)
+
/*
* GPIO settings
*/
#define CONFIG_SYS_GRER1_VAL 0x00000000
#define CONFIG_SYS_GRER2_VAL 0x00000000
#define CONFIG_SYS_GRER3_VAL 0x00000000
-#define CONFIG_SYS_GFER0_VAL 0x00000000
+
#define CONFIG_SYS_GFER1_VAL 0x00000000
-#define CONFIG_SYS_GFER2_VAL 0x00000000
#define CONFIG_SYS_GFER3_VAL 0x00000020
+#if CONFIG_POLARIS
+#define CONFIG_SYS_GFER0_VAL 0x00000001
+#define CONFIG_SYS_GFER2_VAL 0x00200000
+#else
+#define CONFIG_SYS_GFER0_VAL 0x00000000
+#define CONFIG_SYS_GFER2_VAL 0x00000000
+#endif
#define CONFIG_SYS_PSSR_VAL 0x20 /* CHECK */
#define CONFIG_SYS_MSC0_VAL 0x4df84df0
#define CONFIG_SYS_MSC1_VAL 0x7ff87ff4
+#if CONFIG_POLARIS
+#define CONFIG_SYS_MSC2_VAL 0xa2697ff8
+#else
#define CONFIG_SYS_MSC2_VAL 0xa26936d4
+#endif
#define CONFIG_SYS_MDCNFG_VAL 0x880009C9
#define CONFIG_SYS_MDREFR_VAL 0x20ca201e
#define CONFIG_SYS_MDMRS_VAL 0x00220022
#define CONFIG_SYS_MCIO1_VAL 0x0000c108
#define CONFIG_DRIVER_DM9000 1
-#define CONFIG_DM9000_BASE 0x08000000
+
+#if CONFIG_POLARIS
+#define CONFIG_DM9000_BASE 0x0C800000
+#else
+#define CONFIG_DM9000_BASE 0x08000000
+#endif
+
#define DM9000_IO CONFIG_DM9000_BASE
#define DM9000_DATA (CONFIG_DM9000_BASE+0x8004)
/* write flash less slowly */
#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1
+/* Unlock to be used with Intel chips */
+#define CONFIG_SYS_FLASH_PROTECTION 1
+
/* Flash environment locations */
#define CONFIG_ENV_IS_IN_FLASH 1
#define CONFIG_ENV_ADDR (PHYS_FLASH_1 + CONFIG_SYS_MONITOR_LEN) /* Addr of Environment Sector */