CONFIG_SYS_SPL_MALLOC_SIZE + \
SPL_MALLOC_F_SIZE + \
KEYSTONE_SPL_STACK_SIZE - 4)
-#define CONFIG_SYS_SPI_U_BOOT_OFFS CONFIG_SPL_PAD_TO
/* SRAM scratch space entries */
#define SRAM_SCRATCH_SPACE_ADDR CONFIG_SPL_STACK + 0x8
/* UART Configuration */
#define CONFIG_SYS_NS16550_MEM32
-#if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_DM_SERIAL)
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE -4
-#endif
#define CONFIG_SYS_NS16550_COM1 KS2_UART0_BASE
#define CONFIG_SYS_NS16550_COM2 KS2_UART1_BASE
/* SPI Configuration */
#define CONFIG_SYS_SPI_CLK ks_clk_get_rate(KS2_CLK1_6)
-#define CONFIG_SYS_SPI0
-#define CONFIG_SYS_SPI_BASE KS2_SPI0_BASE
-#define CONFIG_SYS_SPI0_NUM_CS 4
-#define CONFIG_SYS_SPI1
-#define CONFIG_SYS_SPI1_BASE KS2_SPI1_BASE
-#define CONFIG_SYS_SPI1_NUM_CS 4
-#define CONFIG_SYS_SPI2
-#define CONFIG_SYS_SPI2_BASE KS2_SPI2_BASE
-#define CONFIG_SYS_SPI2_NUM_CS 4
-#ifdef CONFIG_SPL_BUILD
-#undef CONFIG_DM_SPI
-#undef CONFIG_DM_SPI_FLASH
-#endif
/* Network Configuration */
-#define CONFIG_BOOTP_DEFAULT
-#define CONFIG_BOOTP_DNS2
-#define CONFIG_BOOTP_SEND_HOSTNAME
#define CONFIG_NET_RETRY_COUNT 32
#define CONFIG_SYS_SGMII_REFCLK_MHZ 312
#define CONFIG_SYS_SGMII_LINERATE_MHZ 1250
#define CONFIG_SYS_NAND_MASK_CLE 0x4000
#define CONFIG_SYS_NAND_MASK_ALE 0x2000
#define CONFIG_SYS_NAND_CS 2
-#define CONFIG_SYS_NAND_USE_FLASH_BBT
#define CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST
#define CONFIG_SYS_NAND_LARGEPAGE
"tftp_root=/\0" \
"nfs_root=/export\0" \
"mem_lpae=1\0" \
+ "uinitrd_fixup=1\0" \
"addr_ubi=0x82000000\0" \
"addr_secdb_key=0xc000000\0" \
"name_kern=zImage\0" \
"addr_mon=0x87000000\0" \
- "addr_non_sec_mon=0x0c087fc0\0" \
- "addr_load_sec_bm=0x0c08c000\0" \
+ "addr_non_sec_mon=0x0c097fc0\0" \
+ "addr_load_sec_bm=0x0c09c000\0" \
"run_mon=mon_install ${addr_mon}\0" \
"run_mon_hs=mon_install ${addr_non_sec_mon} " \
"${addr_load_sec_bm}\0" \